Multisim to Ultiboard Transfer Glitch

[CDM]

Hi,

We have made numerous PCBs using Multisim as our schematic capture software and Ultiboard for layout. The latest board came back nonfunctional because the netlist on the schematic is inconsistent with the netlist in the layout for one single part (which is used multiple times on the board). Not only are all of the pins switched, but one of the pins is altogether unconnected. Since all 8 pins are connected on the schematic side, this is clearly not simply an issue of mixed up pin number, but when I forward annotate, it says no differences were detected.

I went through and double and triple checked the symbol, the footprint, and the pin mapping, and everything is correct. As a control, I created a new schematic with nothing but the part in question, and transferred it to Ultiboard, and everything was correct.

Has anyone experienced this issue before? Is this a known glitch, and are there any workarounds or best practices to avoid something like this occuring in the future (apart from disregarding the ratsnest altogether and routing by hand).

Thanks in advance for the help!

[_user32 · Accepted solution]

CDM,

Please contact our support group.   You should not be seeing this issue in v11.0.   I am not aware of any large issues with back/forward annotation since we redesigned the annotation capability and improved the reliability in v11.0 (from 10.1).  

http://sine.ni.com/apps/utf8/nicc.call_me   ->  choose Request Support

Regards,

Pat Noonan

[CDM]

Thanks for the reply. I got in contact with support and sent them the files in question. I will update this thread when they respond.

[FromMars]

I had a similar problem recently with 11.02, made changes to schematic but forward annotation didn't change nets in UB. I was able to work around by deleting nets in UB using its netlist editor, then forward annotating.

[dbur]

Me too. Tech support fixed my file, though I haven't yet verified that, since in the process I lost all my HB refdes assignments and haven't had a chance to go back through them.  I fixed the board by manually editing the netlist in UB and doing some tough re-work on the boards.

I may be full of beans, but it seems a lot of things are funny if you open a design that was done in V10 in V11.  I had a sheet template I used for all my design starts that was made in V10 (or earlier?). Sometimes I start with a previous similar design that might have been a V10 design originally.  This caused me all kinds of grief trying to get HB's/SC's and bus connections and splitters working in a sane manner.  I don't know if it is related to the forward annotate errors.

I have resolved never continue a V10 design in V11.  Open a fresh V11 sheet and copy and paste what you need into it.  So far I haven't seen a problem with that (fingers crossed).

I have a very large design that will be sent out for layout (in another layout tool) that is in progress now.  A netlist export error on this will be a disaster into the 10's of thousands of dollars range.  How will I know if my netlist is exporting correctly without doing the design first myself in UB and manually checking the signals on every pin?  (about 3000 of them)

Another thing, ALWAYS delete the nets in UB (netlist editor) before importing an update from MS.  I hope this gets fixed soon, but it's a fairly easy work around, just don't forget.

Interestingly enough, I have been using MS since V6 and I have never seen a forward annotate error until V11.