Problem building J-K Flip-Flop out of gates and other circuits

[Crazyb]

Hey

I've been having problems with Multisim 11.0 when ever I try building a J-K Flip-Flop out of gates .
The simulation stops at the fourth clock and doesn't want to set Q low, I've seen the error in other design were multisim  doesn't want to do the logic operations.
Multisim seems to have problem were whenever there is a wire that splits from an outputs to two inputs, I've used the measurement probe on an other design and it shows that when ever there is a spilt the simulation it say its state is unknown...... Well I jus found out that when I put a probe on the schematic and status the simulation then it works perfectly 

The picture should explain a lot more 
 

I hope you can understand what my problem is 

If I could get a solution to This problem(s) it would be great because I would like to be able to make more circuits without using several hours of trouble shooting only to come to the conclusion that it should probably work even though the simulation says no...

This would save a lot of time when I'm building those circuits in school and I would be able to make bigger circuit simulation 

[Mahmoud_W]

Hi,

Can you please upload your design file and i'll try to troubleshoot it for you.

Regards,

Mahmoud W

National Instruments

[Crazyb]

Wasn't the design file attached?
 I'll try to attach all the design just to be sure...
But the design that I really wish to get working correctly is the JK flip flop