SR latch receives set signal with conditions not met

[egornovice]

Good day everyone!

I'm having this problem where an AND gate behaves normally when connected to an indicator and not so much when connected to a SR latch's set pin. Please, take a look at these pictures:

As you can see here, the X5 indicator is off because U8 doesn't pass the current because of unmet condition yet when I connect U8 to U5, it sets U5's state to 1:

[GGoodwin]

Hi egornovice,

Why not create a simple circuit where you can test if the S-R Latch is working properly. If you will do this, use two SPDT switches, one for SET and one for RESET. The switches will connect to +5 V (V+ or Vcc) in one position and to ground (GND) at the other position.

Best regards,

G. Goodwin

[egornovice]

The latch itself works just fine when we send the SET/RESET signals manually. Turns out, even adding the grounds isn't necessary for the simulation at least:

What's funny is when you put an additional switch (S1), then start the simulation, turn the switch on, everything starts working just fine because no wrong signal was sent from U8 to U5 at the start of the simulation. Here, take a look:

Sadly, the "workaround" isn't helpful as it needs to be automatic and I'm going to add a lot of other logic which also needs to work on its own.

[egornovice]

Perhaps this will give us a clue:

Spoiler

When sending a constant "0" to U8's lower leg, we can see that everything works normally. So, something must be sending a positive signal to the lower leg but I have yet to find out what causes that.

This works fine, too:

Spoiler

[GGoodwin]

I appreciate your informative replies and I understand what you obtained in simulation with those images. I don't have the application Multisim (Desktop), I only use Multisim Live (Free Subscription) so I cannot perform further experiments with your circuit. I can only suggest alternative workaround which might be acceptable for your objective.

For U8, you can try using other AND gate from the library. The purpose of this is to test and avoid any problem associated with the AND gate that you currently use. You can also try replacing U8 with a three-input AND gate but connect the third input to Vcc (+5 V).

Forcing the output of the AND gate to logic 0 briefly at the start of simulation is also a workable idea. Refer to the modification below

Vinit is a Step Voltage with a Step time of 1 ms (adjust when necessary). This brings the "automatic" sense of initializing the output of AND gate U8 and it is more suitable than using a clock.