Unexpected AND gate behavior

[egornovice]

(the V+ gives 12V)

Hello! I'm a novice and wondering why I'm getting 2.5V at the U6's output pin. As far as I know, an AND gate should not let any current unless both inputs are positive. Would appreciate your help!

[Pater_Mater_Filius]

Hello egornovice,

If you are using the AND (or other Logical operators) you have to connect both inputs. Otherwise, it goes to an "undefined stage" which can return a wrong value.

I replicated the scheme to show you the difference.

In this case, there is nothing connected to the second input of the AND operator. But as I connect it to the ground everything works as it should (shown in the picture below).

As a result, I suggest grounding the inputs if you are not going to use them, this will make your scheme work rightly.

Best Regards,

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P.S. If the content was useful please hit the KUDO button to let me know 😉

[GGoodwin]

Hi egornovice and Pater_Mater_Filius,

The AND gate produced an output of 2.5 V because one input is floating (disconnected). Multisim uses 2.5 V as the output voltage level corresponding to indeterminate logic state if 5 V is the implied power supply of logic gates. Regarding the simulation result, this is not the behavior of real-world logic circuits, consider the following:

• Real-world logic gates will only go to stable mid-supply voltage if the gate has three-state capability, put into this floating/high-impedance state, and the output node is driven to the mid-supply voltage by other device(s) or component(s). You may open the circuit CMOS (Noninverting) Three-State Gate (Series Output Driver) to see an example where the resistive divider puts the output node to mid-supply voltage when the gate's output is disabled. Real-world logic gates with no three-state output capability can only go to voltage level corresponding to logic 0, go to voltage level corresponding to logic 1, or oscillate between logic 0 and logic 1 voltage levels. The output should not settle to stable mid-supply voltage.
• Some logic families, particularly those using bipolar transistors, will recognize floating input as logic 1. Nevertheless, leaving an input terminal floating is not recommended and is not a good practice.

Basically input voltages exceeding the power supply voltage level should be avoided. If the AND gate is powered from +5 V, directly applying +12 V at the input will likely cause damage to the logic gate, breadboard/protoboard, or equipment/material used for this circuit. There are of course newer logic gate families which are designed to tolerate input levels greater than its power supply voltage. However, a 12-Volt-tolerant 5-Volt logic gate is quite not common.

LEDs should not be connected directly to logic gate output, which are generally voltage sources (can be modeled by an ideal voltage source in series with a very low resistance).

Experiment with both input terminals connected to V+ and observe how enormous the current from the AND gate to the LED is,

Use a current limiting resistor in series with the LED, try 200 Ω to 330 Ω. You may open Re: SPDT switch voltage drop for a related discussion.

Best regards,

G. Goodwin

[egornovice]

Thank you very much!

[GGoodwin]

In my previous reply I brought up the simulation behavior of logic gates with no three-state capability. The problem presented in this post and the subsequent reply evoked the result of an experiment I conducted previously. This was when logic gates and digital simulation was just recently introduced to Multisim Live. My simple experiment involves a signal with very slow rise/fall time driving a logic gate. Because the output is set to mid-supply voltage when a relevant input goes to indeterminate voltage range, it causes the output to abruptly jump from a logic 0/1 voltage level to indeterminate state level. Driving the output to mid-supply voltage outright provides us with a quick and simple way of handling indeterminate input levels. However, the abrupt transition can severely affect or totally ruin the simulation result of some circuits.

The outcome of my experiment influenced my thoughts when I was composing my first reply. However, as I needed to leave the forum already for that day, my endeavor to quickly complete my message resulted to flawed information in one part of my post. Real-world logic gates can be biased so that the output goes to indeterminate voltage level. They can be deliberately configured for this state for possible use as high-gain AC amplifier, for example. A logic gate output can also go to indeterminate state through unintentional means such as inappropriate values of input resistors or floating pin. We just note that a floating input can make the logic gate behave somewhat differently as noise couples easier than in the case when the input is driven through a lower resistance. What I really perceive as a woe is the abrupt transition I described in the first paragraph.