Urgent! reading DDF files from UB v5, copper area problems

[stressed_user]

Hi,

I have a very strange problem with Ultiboard.

When reading an old DDF file (v5), it is opened and converted to ewprj...

I have no schematic file (just a paper version) and no netlist...

Some obsolete footprints need to be changed to newer ones...

so far no problem, I inserted everything manually...

it is a four-layer board with multiple copper areas on the inner-layers.

When exporting gerber data RS274X, then the weardest things happen...

Via's that should be attached to GND are attached to +5V

 I found that while checken old and new gerbers with GCprvue....

So I checked the design:

the settings for all copper area's are correct! eg: copper area onthe inner layers are set as follows

Inner1: GND layer, enable voiding, connected to net GND, no thermal reliefs for the via's

Inner2: +5V layer, enable voiding, connected to net +5V, no thermal reliefs for the via's

but when checking, the GND layer isn't connected to the GND via's, but the 5V layer is... 

 ! there is a void in the GND layer while there shouldn't, and the 5V layer is connected,

And the strangest thing: when running a DRC check, you get all the faulty connections!

when looking at the original file, after I just opened it, then everything is ok...

maybe this will give a clue as well:

sometimes, for no apparent reason, there is no more fill-style in a copper area, it has dissapeared.

all you see is the outline of it...

From the moment you start working on the original design, things go wrong....

Can anyone from NI check this one out? This happens quite often in design-updates...

I use UB version 10.0.343

the attachment are screnshots with GND (green layer) and 5V (blue layer) settings...

Johan

[hgregg]

Is each via assigned to the correct net? Edit the via properties and use Assume net... 

I'm not sure if that will help you or not, but I've had strange problems with vias connecting and disconnecting themselves if the net is not assigned. After placing a via it doesn't seem to remember the net unless you go back and set it in the properties. 

Hg

[stressed_user · Accepted solution]

Hi, No, via's should be assigned to the net (trace) they are placed in, never found any problem with this... But the best news: I finally found the problem, after many hours of searching.... I allready mentioned that there was no more fill-styme in a number of copper area'... well that's how I finally found the problem... On one side of the board I had to replace an 16 pin PDIP by a 4 pole through hole connector. In the 5V inner layer , the original designer layed all necessary tracks connecting all 5V connections together... One of those tracks (which you can not see when the fill-style is full) was touching one pin of the new through hole connector. Thus connected to the 5V, and this pin had to be ground in the updated design... thus causing a short-circuit... a short between those layers apparantly caused all via's of the 5V to be connected to GND on the complete board... That made it very hard to find the problem.... Only after I changed the fill-style to 'no-filling' I could find the connection... Can NI find a way to find this problem easier? when having DRC faults all around the board , it is hard to see which one actually really causes the error Best regards Johan