Various issues with Ultiboard 12

[Kleven]

Hi,

As I mentioned in another conversation, I'm going to list a few problems that I have had in a new discussion thread.

1.  I had a previous issue with trace properties and wanted to check on the status.  Here's a link:  http://forums.ni.com/t5/Circuit-Design-Suite-Multisim/Possible-Ultiboard-bug-re-trace-properties-12-...

2.  Automatic trace width using Place->Line : Occasionally the automatic trace width (necessary if you want to be able to quickly modify trace widths by changing the net trace width property in the spreadsheet view) will select a trace width that is not correct for the net that is being routed.  I have not been able to characterize a set of repeatability criteria.  If necessary I can provide my project file but would prefer to email it.  A little more description:  I have nets with defined trace widths of 130um and 250um (power/gnd).  When I use Place->Line to route traces occasionally the pwr/gnd nets will only be 130um and sometimes one of the signal nets will be 250um.  After routing the trace I can go to the net spreadsheet tab and change the trace width of the net in question and the offending trace will be changed to the new width.  Due to this, this isn't a showstopper, but it's a serious drain on productivity.

3.  Non-plated holes and solder mask:  The board shop I'm planning to use wants solder mask relief over non-plated holes. Is there any built-in way to do this?  I realize I can simply draw a shape on the solder mask top and bottom layers, but it would be much better if this was a feature of the hole itself like it is for vias.  I don't want to go and add solder mask shapes in my part library until I know for certain that this is the only way to accomplish this.

I will try to add more later, but this is all I can recall at the moment.

Thanks,

Kleven

[Tien_P]

HI Kleven,

1.  I just checked V12 and it is still the case.  I've re-enter this as a CAR and the ID is: 390079

2.  If you can PM me with the file I can look into it.  On the spreadsheet view select the Nets tab and see if changing the max/min width will help.  There is a feature known as necking and the purpose of this is when you are routing between two objects, the trace will neck down to prevent the DRC error.    Select Options»Global Preferences»PCB Design, see if the Narrow traces during routing is checked

3.  Creating a component with just a hole and then manually adding a soldermask is the only way. I will create a feature request for this.

[Kleven]

Thank you for your reply Tien.

I checked my routing settings and the mix/max width are set as expected (less than 130 and greater than 250) and the narrow option in global preferences is not selected.

It's possible there is some kind of netlist or file corruption.  I say that because when I am in Place->Line mode and I click on a via that is connected to the GND net I see white X's on neighboring signal pads.  Prior to a recent forward annotation, that via was actually connected to those nets.

That brings me to one other issue I've had repeatedly with Ultiboard 11 and 12 - forward annotation problems.  In Ultiboard 11, sometimes the netlist would just become scrambled after forward annotation.  Lots of 'leftover' pin/net connections that sometimes would get resolved after a second pass of annotating the file and sometimes would never get corrected - Ultiboard would say that everything matched the annotation file when it clearly didn't.

In Ultiboard 12, I've had repeated issues with program crashes when forward annotating.  I've had to restart my layout from scratch three times because I couldn't find the offending item in the design.  I tried deleting the netlist and that didn't seem to work.  I tried deleting various parts hoping that would do the trick but I rarely found the culprit.

At one point it seemed that a particular mult-section component was causing the problem but I have no proof.  Plus, I had crashes before that component was even in the design.

I will PM you the file.