Why doesn't the mosfet simulate correctly?

[dbur]

I read Vgs as "Voltage from gate to source" or "Voltage at source, referenced to gate"

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Well you can't have it both ways.  "Voltage from gate to source" is correct, not the other one.  Negative for p chan @ Vth, positive for n channel.

Don't take my word.  Open up any p/n channel mosfet datasheet and look how they characterize and specifiy the gate voltage characteristics.  After all that's the spec convention we have to work with.

[RnDMonkey]

Ok, let's look at it at the simplest level. Maybe I'm backwards on one of the most basic conventions in electronics, in fact I probably am. If you wanted to measure Vgs, wouldn't you connect the black lead on a multimeter to the gate and the red lead to the source? Isn't that what is meant by "FROM gate TO source"?

[RnDMonkey]

As I suspected, I was backwards. Funny how flipping a fundamental concept of electronics makes the whole thing fall apart. Anyway, it seems silly to say "Voltage from gate to source" when what you mean is "Voltage at gate, with reference to source". I think of a logical direction when you say "Voltage from gate to source" where you start from the gate and move to the source, where you would find a higher voltage. In my mind this equals a positive voltage since if you start at gate and move to source you have increased voltage, not decreased.

[dbur]

To me what you are saying is backwards.  If I want to measure or specify gate voltage with respect to source the black wire goes on the source.  Anyway this is becoming an academic semantics(sp?) discussion and no matter what you conclude you still have to deal with the convention as applied in every mosfet data sheet.  P channel gate threshold voltage is negative with respect to source.  N channel gate threshold is positive.
David B

[RnDMonkey]

It is symantics, really. Vgs should read "Voltage at gate with reference to source".

[lacy]

I don't mean to interject here, but maybe a simplistic analysis would help. Think of a PNP Transistor and the way it is hooked up with the emitter more positive than the base..As the voltage goes more negative with respect to the emitter the transitor conducts more. The same can be applied to JFET or MOSFET. With enhancements it is a little more difficult to visualize this. With 0V on the base the depletion layers keeps the FET in the off state untill the appropriate voltage is applied to "open" the channel for current to flow.

Also, on any FET the drain and source are interchangeable and that can be confusing when examining a circuit. You have to keep in mind the type of FET (P-Channel or N-Channel) you have and then determine which connection is the drain and which is the source based upon that knowlege.

This is how I keep it straight in my head. I do believe my thinking to be correct here.

I was trained to look at things in the simplest form and maybe my simplistic way of looking at things has been of help here

[RnDMonkey]

The way I'm using to remember the drain and source on eMOSFETs is that the drain on a PNP is toward the more positive voltage source/supply/whatever. For NPN, the drain is toward the more negative source/supply/ground/whatever. I'm not sure what you meant by the drain and source being interchangeable. Lacy, I think one of us is confusing PNP with NPN, because doesn't a PNP require the gate (base) to be more positive than the source (emitter)? Therefore as the voltage goes more positive with respect to the source (emitter) the transistor conducts more? /facesmash

[lacy]

"PNP require the gate (base) to be more positive than the source (emitter)"

Wrong. A PNP requires the base to be more negative than the emitter. Most circuit have the emitter tied to positive. The N in the name is a clue at to which way the voltage need to go in order for conduction the occur. The opposite is true for NPN (P for postive on the base).

"I'm not sure what you meant by the drain and source being interchangeable"

The drains and sources in FETs can be flipped in the circuit and it will still operate the same. Nothing really changes except that instead of PIN1 being the source and PIN3 being the drain according to the datasheet, they are flipped A good designer would probably never do this swap. If they have done so, then the material that the FET is made of will clue you in on the proper label for the pins. I didin't mean to cause confusion on this one as the point I was trying to make is that the material that a Transistor or Fet is made of will clue you in on which is the emitter/source, base/gate, or drain/collector.

I hope I have cleared up my pouints I was trying to make. If need be I can find a resource on the internet that may be able to explain this better than I can. I am not the best person when it comes to explaining anything. I can see it in my head, but have a hard time getting it to paper.

[RnDMonkey]

I think I was in error when I compared BJTs with FETs. Multisim does not like you to wire a FET the same way you wire a BJT. If you wire an NPN FET with the Source toward ground and the Drain to VCC, the FET will always be on (note the now-forward-biased diode across drain-source). With a BJT in a common-emitter arrangement, you actually WOULD wire it up with the Emitter to ground and the Collector toward VCC.

So when you reverse the leads on a FET, you have to move your load resistor to the ground side so it is still on the drain terminal. If you leave it on the source, you  have a source-follower, as David corrected me on.

Now that you have source tied high instead of low, the voltage transition has to move in the opposite direction. Instead of being off at 0V and on at 5V, for example, you are now off at 50V and on at 45V (if you have your supply is 50V), which is more negative (less positive) with respect to source. See attached file for a comparison.

[lacy]

First, the FET in you schematic was not an N-Channel Fet. It was a P-Channel Fet. So to me your comparison wouldn;t work. You have to compare NPN BJT to N-Channel Fets and PNP BJT to P-Channel FETS.

I have included in this post a rather crude hook up for the FETs. They are arranged the same way you would normally hook up a NPN BJT and a PNP BJT. I have added text to it to explain what I am seeing. Notice that I have the source of the P-Channel tied high through the resistor while I have the Drain of the N-Channel tied high throught the resistor. Flip the switches and see what happens.

Now what could be occurring here is the difference of where we are taking our measurements from. You are taking it off the resistor tied to ground and I am taking mine from the resitor tied to +V. This would create an inversion of our results and that might be what is confusing us.

I am not saying I am right and I am not saying you are wrong, but I would like to find out more and I am going into research mode to further investigate this just so I can be satified even if I am wrong.