FIFOを使ったオシロスコープを作りたい

yoshi-k · ‎05-31-2018

FPGAからHOSTへFIFOに、アナログ入力からの信号をそのまま送り、HOSTで波形グラフを用いて波形を表示するプログラムを作りたいです。

最小値0V、最大値10Vの正弦波を入力して、HOST側では0～4095の整数として受け取りたいです。

そのため、アナログ入力の値を409.5倍してから、FIFOに入れています。FIFOのデータタイプはI32です。少数は四捨五入してくれるはずです。

コンパイルするとエラーが起きてコンパイルできません。

なぜでしょうか。

よろしくお願いします。

エラーメッセージ

LabVIEW FPGA: Xilinxのエラーによりコンパイルに失敗しました。

詳細:
ERROR:HDLCompiler:410 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\NiFpgaAG_00000002_WhileLoop.vhd" Line 182: Expression has 66 elements ; expected 50
Netlist NiFpgaAG_00000002_WhileLoop(vhdl_labview) remains a blackbox, due to errors in its contents

Elaborating entity <whileloop> (architecture <rtl>) with generics from library <work>.

Elaborating entity <InvisibleResholder> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9233DoSyncRes> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9233SyncResource> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <Crio9233SyncResAcqData> (architecture <rtl>) with generics from library <work>.

Elaborating entity <TopEnablePassThru> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Interface> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\Interface.vhd" Line 93: Using initial value (('U','U',"UUUUU")) for birqoutarray since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\Interface.vhd" Line 95: Using initial value ("UU") for birqstatusoutarray since it is never assigned

Elaborating entity <MiteInterface> (architecture <rtl>) from library <work>.

Elaborating entity <MiteInterfaceOutputEnables> (architecture <rtl>) from library <work>.

Elaborating entity <RegisterAccess> (architecture <rtl>) with generics from library <work>.

Elaborating entity <RegisterAccess32> (architecture <rtl>) with generics from library <work>.

Elaborating entity <MiteDmaComponent> (architecture <rtl>) with generics from library <work>.

Elaborating entity <MiteDmaComponentEnableChain> (architecture <rtl>) with generics from library <work>.

Elaborating entity <TimeoutManager> (architecture <rtl>) with generics from library <work>.
INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\MiteDmaComponentEnableChain.vhd" Line 221. Case statement is complete. others clause is never selected

Elaborating entity <NiFpgaFifoClearControl> (architecture <rtl>) with generics from library <work>.
INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\NiFpgaFifoClearControl.vhd" Line 229. Case statement is complete. others clause is never selected

Elaborating entity <DoubleSyncBool> (architecture <behavior>) from library <work>.

Elaborating entity <DoubleSyncBase> (architecture <behavior>) with generics from library <work>.

Elaborating entity <NiFpgaFifoPortReset> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaPulseSyncBaseWrapper> (architecture <rtl>) from library <work>.

Elaborating entity <PulseSyncBase> (architecture <behavior>) from library <work>.

Elaborating entity <PulseSyncBool> (architecture <behavior>) from library <work>.

Elaborating entity <MiteDmaInput> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaMiteReadInterface> (architecture <RTL>) with generics from library <work>.

Elaborating entity <NiFpgaFifo> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaFifoFlags> (architecture <rtl>) with generics from library <work>.

Elaborating entity <SyncFifoFlags> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopUnsigned> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopGray> (architecture <rtl>) with generics from library <work>.

Elaborating entity <GenDataValid> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopBoolVec> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopSLV> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaDualPortRAM> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaDualPortRAM_Inferred> (architecture <rtl>) with generics from library <work>.

Elaborating entity <FifoReadAdapter> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\PkgNiUtilities.vhd" Line 403: Range is empty (null range)
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\FifoReadAdapter.vhd" Line 87: Range is empty (null range)
WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\FifoReadAdapter.vhd" Line 195: Net <StallDisableBlk.cStallDisableLoc> does not have a driver.

Elaborating entity <HandshakeBool> (architecture <struct>) from library <work>.

Elaborating entity <HandshakeBase> (architecture <behavior>) with generics from library <work>.

Elaborating entity <DFlopSlvResetVal> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DmaDisabler> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CpuDataRd> (architecture <rtl>) from library <work>.

Elaborating entity <DmaMiteReadRegs> (architecture <RTL>) with generics from library <work>.

Elaborating entity <NiFpgaFifoCountControl> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\MiteDmaComponent.vhd" Line 90: Net <bDataOutFromFifo[15]> does not have a driver.

Elaborating entity <MiteIrq> (architecture <rtl>) from library <work>.
INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\MiteIrq.vhd" Line 337. Case statement is complete. others clause is never selected

Elaborating entity <HandshakeBaseResetCross> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopSlvResetVal> (architecture <rtl>) with generics from library <work>.

Elaborating entity <ResetSync> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopBool> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlop> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopBoolFallingEdge> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopFallingEdge> (architecture <rtl>) with generics from library <work>.

Elaborating entity <ResetSync> (architecture <rtl>) with generics from library <work>.

Elaborating entity <HandshakeBaseResetCross> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopSlvResetVal> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\Interface.vhd" Line 75: Net <DmaClkArray[1]> does not have a driver.
WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\Interface.vhd" Line 76: Net <DmaRwEnableInArray[1]> does not have a driver.
WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\Interface.vhd" Line 78: Net <DmaRwEnableOutClearArray[1]> does not have a driver.
WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\Interface.vhd" Line 79: Net <DmaRwDataInArray[1][15]> does not have a driver.
WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\Interface.vhd" Line 81: Net <DmaRwTimeoutArray[1][31]> does not have a driver.
WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\Interface.vhd" Line 84: Net <DmaCtEnableInArray[0]> does not have a driver.
WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\Interface.vhd" Line 86: Net <DmaCtEnableOutClearArray[0]> does not have a driver.
WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\Interface.vhd" Line 91: Net <IrqClkArray[0]> does not have a driver.
WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\Interface.vhd" Line 96: Net <mIpIrqVec[0]> does not have a driver.

Elaborating entity <bushold> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\bushold.vhd" Line 131: Assignment to adiagramreset ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\bushold.vhd" Line 214: Assignment to miteclkwidewrite ignored, since the identifier is never used

Elaborating entity <NiFpgaRegFrameworkShiftReg> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DoubleSyncBoolAsyncIn> (architecture <rtl>) with generics from library <work>.

Elaborating entity <IDSel_Timer> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <Crio9233Resource> (architecture <struct>) with generics from library <work>.

Elaborating entity <Crio9233ResourceCore> (architecture <struct>) with generics from library <work>.

Elaborating entity <Crio9233> (architecture <rtl>) with generics from library <work>.

Elaborating entity <EnableChainSM> (architecture <rtl>) from library <work>.

Elaborating entity <EnableChainWithTimeout> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRioStock> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRioStockModuleId> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRioStockModeSelector> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRioStockSpiEngine> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRioStockEePromRead> (architecture <rtl>) from library <work>.

Elaborating entity <Crio9233EnableChainHandler> (architecture <rtl>) from library <work>.

Elaborating entity <CrioEepromRead> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9233IoHandler> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRio9233GetCalConst> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRio9233CalData> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRioCalMultiply> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRioCalMemory> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRioCalParallelCrc> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CrioParallelCrcCore> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9233ConfigurationHandler> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\Crio9233ConfigurationHandler.vhd" Line 200: Range is empty (null range)

Elaborating entity <CcMuxSL2> (architecture <RTL>) with generics from library <work>.
WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\CcMuxSL2.vhd" Line 46: <lut6> remains a black-box since it has no binding entity.

Elaborating entity <Crio9233AdcSyncHandler> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\Crio9233.vhd" Line 954: Assignment to ctedsreqmode ignored, since the identifier is never used

Elaborating entity <CrioClockCondition> (architecture <rtl>) from library <work>.
WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\CrioClockCondition.vhd" Line 34: <fdc> remains a black-box since it has no binding entity.
WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\CrioClockCondition.vhd" Line 44: <fdc_1> remains a black-box since it has no binding entity.

Elaborating entity <ViControl> (architecture <rtl>) with generics from library <work>.

Elaborating entity <SafeBusCrossing> (architecture <rtl>) with generics from library <work>.
INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\SafeBusCrossing.vhd" Line 215. Case statement is complete. others clause is never selected

Elaborating entity <HandshakeBaseResetCross> (architecture <rtl>) with generics from library <work>.
INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\ViControl.vhd" Line 562. Case statement is complete. others clause is never selected

Elaborating entity <DiagramReset> (architecture <rtl>) with generics from library <work>.

Elaborating entity <SafeBusCrossing> (architecture <rtl>) with generics from library <work>.
INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\SafeBusCrossing.vhd" Line 215. Case statement is complete. others clause is never selected

Elaborating entity <HandshakeBaseResetCross> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopSlvResetVal> (architecture <rtl>) with generics from library <work>.
INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\DiagramReset.vhd" Line 710. Case statement is complete. others clause is never selected

Elaborating entity <ViSignature> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio80MhzClkRes> (architecture <struct>) from library <work>.
INFO:TclTasksC:1850 - process run : Synthesize - XST is done.

Elaborating entity <Sleep> (architecture <behavioral>) with generics from library <work>.
WARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\Sleep.vhd" Line 76: Assignment to din_enable_clr ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\Sleep.vhd" Line 77: Assignment to din_enable_in ignored, since the identifier is never used

Elaborating entity <CustomArbForTopEnablesPortOnResTopEnablePassThru> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbRW> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\NiFpgaArbRW.vhd" Line 91: Range is empty (null range)
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\NiFpgaArbRW.vhd" Line 92: Range is empty (null range)
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\NiFpgaArbRW.vhd" Line 101: Range is empty (null range)

Elaborating entity <NiFpgaArbRW> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbSerializeAccess> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbPowerOf2> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CustomArbForMiteIoLikePortOnResInterface> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\OLX3C8a_AHOtTZ9\CustomArbForMiteIoLikePortOnResInterface.vhd" Line 53: Assignment to interfaceclockregportin ignored, since the identifier is never used

Elaborating entity <CustomArbFordinPortOnResSleep> (architecture <rtl>) with generics from library <work>.
-->

Total memory usage is 224264 kilobytes

Number of errors : 1 ( 0 filtered)
Number of warnings : 45 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

Process "Synthesize - XST" failed

コンパイル時間
---------------------------
提出された日付: 2018/05/31 20:43
結果を取得した日付: 2018/05/31 20:44
空き待ち時間: 00:06
コンパイル時間: 00:55
- PlanAhead: 00:11
- コア生成: 00:00
- シンセシス - Xst: 00:35

yoshi-k · ‎05-31-2018

新規プロジェクトの空VIで、新たに同じものを作ったら動きました。

NI製品ディスカッション

FIFOを使ったオシロスコープを作りたい

FIFOを使ったオシロスコープを作りたい

Re: FIFOを使ったオシロスコープを作りたい