Engine Simulation Custom Device Feedback

[chigi22]

So-called "Expert" reporting in.

SB: all FXP inputs ("FullyCustomTeeth.Offset", "Crank or Cycle Angle", and "FullyCustomTeeth.Next Angle") to the fully custom generator sub-vi ("AES Fully Customizable Teeth Generation.vi") are 61 bit word length 10 bit integer word length.

- Ross Dunkel

[StephenB]

Hey Ross!

Ok I figured it out. That wasn't the problem but it led me to the problem.

The memory inside that VI is too small to hold that many angles. It is set to 64 elements. You should be able to increase its size to something bigger to avoid the problem.

[chigi22]

Hey SB,

Thanks for the info. What exactly is stored in each memory element? I ask so that I might get a sense for how many elements to try increasing the size to. I'm not really sure Ireally understand what exactly is going on with this bit of code.

Thanks,

Ross

[StephenB]

It stores the angles that the pulse needs to transition. So each edge.

[BKennedy]

Hey again!

New issue popped up, not sure if its a bonehead thing or not, but we are trying to implement 2 fully custom cams as well as a fully custom crank. To get this, I added another Fully Custom template loop in the FPGA code, changed "Cycle Angle" to "Crank Angle", redirected the IO, and changed any indicators from "Cams.Cam1.xx" to "Crank.Crank1.xx". We only need to simulate one crank at this time. However the Crank signal isn't being generated, is there something else i need to do? I have attached the bitfile for further elucidation!

Thanks in Advance,

Bryan

[Devin_K]

I don't see anything wrong with the bitfile, and it seems to load up correctly in system explorer.

One thing I would check though is the code for loading up the teeth data.  Each "Fully Custom" component consists of two loops: a generation loop and a FIFO load loop.  These two loops communicate with a VI-scoped FIFO (by default named "Data FIFO").  Make sure that both components ("Cams" and "Crank") each have their own data FIFO, and reference the correct one in each of your loops.  It's possible that your Crank loops are pointing to the wrong FIFO.  These FIFOs don't show up in the compiled bitfile, so without seeing your VI I can't tell if that's your problem.

[BKennedy]

I did check that! When i plopped the template code down, it created Data FIFO 2. I had to point the methods to that new FIFO, but I did at least that much! Mind if I email you a copy of the VI? Just drop me contact, or preferred distribution, info at my email which should no longer be private.

Thanks!

Bryan

[StephenB]

Hey Bryan,

I'm looking at your code and the first thing I noticed when I opened the code is its loading its dependencies out of vi.lib. This is not correct. The Automotive Engine Simulation installs its components to the user.lib directory not vi.lib. It appears you have a corrupted install. I would remove the offending directory from your computer's vi.lib (back it up somewhere) and reinstall the AES library.

Here is the warning text:

C:\Users\sbarrett\Desktop\FPGA\CAT Midrange HIL FPGA - Fully Custom v10.0 - 7853R.vi (CAT Midrange HIL FPGA - Fully Custom v10.0 - 7853R.vi)

    - The VI expected to be at "<vilib>:\_NI VeriStand FPGA Support\NI VeriStand RIO Library\Custom Device Components\Engine Simulation\Engine Simulation Globals.vi" was loaded from "C:\Program Files (x86)\National Instruments\LabVIEW 2011\user.lib\_NI VeriStand FPGA Support\NI VeriStand RIO Library\Custom Device Components\Engine Simulation\Engine Simulation Globals.vi".

C:\Users\sbarrett\Desktop\FPGA\CAT Midrange HIL FPGA Project.lvproj (CAT Midrange HIL FPGA Project.lvproj)

    - The VI expected to be at "C:\Program Files (x86)\National Instruments\LabVIEW 2011\vi.lib\_NI VeriStand FPGA Support\NI VeriStand RIO Library\Custom Device Components\Engine Simulation\Engine Simulation Globals.vi" was loaded from "C:\Program Files (x86)\National Instruments\LabVIEW 2011\user.lib\_NI VeriStand FPGA Support\NI VeriStand RIO Library\Custom Device Components\Engine Simulation\Engine Simulation Globals.vi".

I don't see anything wrong with the FPGA code... so this is at least something to try.

I'm going to dig into the custom device now and see if I see any issue using two Fully Custom components, but so far I don't...

Can you confirm you set the correct FPGA Simulation Angle Reference in the system explorer for your crank angle? Can you share your crank angles you programmed?

Thanks,

[StephenB]

Yep actually the global is the exact problem. You have modified the global and saved a copy here:

FPGA\Private\Engine Simulation Globals_CATHIL.vi

But our template uses the global we install here:

user.lib\_NI VeriStand FPGA Support\NI VeriStand RIO Library\Custom Device Components\Engine Simulation\Engine Simulation Globals.vi

So your APU updates your modified global but your crank loop uses the other global.

I would suggest fixing this so you use the engine simulation global unmodified and instead make your own global for your own data.

[BKennedy]

Global seems linked OK on this machine. I will go ahead and revert to the shipping Global and use an extra global for the memory lock anyway. It may have been confused during the compile process. Will keep you updated!