Engine Simulation Toolkit Feedback

[ElectricWraith]

This is probably a dumb question, but I'll ask anyways: How am I to access FPGA I/O that's not specific to the EST?

I ask because I had an Engine Simulation Custom Device (VS2012) that I inherited that contained a lot of DIO, PWM, and some AIO. I have upgraded one of my systems to LV2014/VS2014 and have compiled a new bitfile. I deployed a new VS project and the generated crank signal seems to be working. Now I need to access the aforementioned non-EST I/O that was previously handled through the FPGA target configured in the System Explorer window.

If I do this now, it asks me for an FPGA configuration file (which I've been wrestling with all day), but when I deploy it I get the same error someone else posted earlier (FPGA busy in C API mode) that you indicated was caused by two different bitfiles being loaded. I'm not using two bitfiles, but I am using the bitfile and the config file. I'm sure this is the problem, I just need to know how to access the non-EST FPGA resources.

Thanks!

[StephenB]

Hi ElectricWraith,

Not a dumb question!

As you noticed, the engine sim toolkit only involves engine specific I/O. If you need to integrate basic single point I/O like analogs, digitals, PWMs, you can do so through the standard NI VeriStand FPGA interface as you noticed. In fact, if you had this working in NIVS 2012, nothing with this has changed or has anything to do with the Engine Simulation Toolkit. So if it worked then it should work now. You can reuse your same FPGA code (altho now with EST IP) and same .fpgaconfig.

The error you're receiving is because you're .fpgaconfig file is pointing to a different bitfile than you have selected with the Engine Simulation Toolkit custom device.

[ElectricWraith]

OK, I've been using the NI Veristand FPGA Configuration Editor utility in an attempt to create a config file that matches the IO I have in the FPGA VI. I made some updates to that this morning, re-compiled it, and pointed the EST in my VS project at the new bitfile. I deleted the existing FPGA target, which was pointed at the different bitfile, and now when I try to add a new target using my newly created config file, I get this error:

For starters, none of the packets I have created exceed 64 bits. If I delete the 11th packet, I get the same error but it's griping about the 10th packet, then the 9th, etc. I have no idea what I'm doing incorrectly here.

edit: No idea why this message posted three times and gave me an error each time, but I deleted the extras. I messed around with things a bit more on Friday and I think that the problem somehow comes from improperly formatted XML as a result of using the Veristand FPGA Configuration Editor utility, but I still have no idea why.

[JianZ]

Hi Stephen,

I noticed your reply above about realizing PWM measuremeng and output using FPGA. But when I was implementing the add-on:FPGA XML Builder Node, I found that Veristand will require a .fpgaconfig file as well as a .lvbitx file. But the .lvbitx file must be the same as the one used for engine simulation toolkit.

From my trials, it seems that the PWM function will only work if the .lvbitx file is built for the PWM vi but not for the EST vi. Does that mean that we cannot use EST with other FPGA vi/functionalities? Do we have to incorprate all other functionalities in EST vi as well?

Thanks

Jian

[StephenB]

Hi JianZ, EST should not interfere with any other FPGA code or features you use. Indeed, you can use the same bitfile with EST as well as with an fpgaconfig file. Just put both EST code and other code in your FPGA VI and write your fpgaconfig as normal. What problems are you experiencing?

[JianZ]

Hi Stephen,

I had a separate project with only PWM functionalities and I generated the fpgaconfig file and its own lvbitx file(and it seems that the two files must have the same name). And they worked when I created a new Veristand project. But if I just load a fpgaconfig file in Veristand without corresponding lvbitx file, therre will be an error about parsing issues(it is not able to parse the info in the fpgaconfig file). If I just load the fpgaconfig file that works separately in my original project that includes EST, there will be an error during deploymeng saying that the FPGA is busy operating in FPGA interface C API mode.

If I want to use EST separately with other FPGA(under hardware category) functionalities in VS, what procedure should I follow to complie a lvbitx file that is compatible for both? Since the compliation of lvbitx file requires users to specify a vi, I am not sure that the same lvbitx file will work for both.

[StephenB]

Hi JianZ,

The only way you could be getting that error is if you're using two different bitfiles.

I've made a few slides of the procedure. Let me know if this helps:

[JianZ]

Hi Stephen,

Thanks a lot for the slides. In slide three, what do you mean by adding EST to new FPGA vi? Does that mean to copy all the codes of EST vi into the custom functionality vi?

If I understand correctly, the 3 slides are procedures for 3 different applications, right?

Thanks

Jian

[StephenB]

Yes the 3 slides are 3 different use cases. The third one is you.

Your FPGA code will have one top-level VI named whatever you want to name it. This is the VI that is compiled into the bitfile and is specified in the build specification. The contents of this VI are up to you. Based upon your description, it sounds like you want PWMs and Engine Simulation inside this VI, so you should copy paste from examples or wherever to place this code inside your top level VI.

-- Stephen Barrett (mobile)

[Suresh@V]

Hi StephenB

I am new to both veristand 2013 and EST toolkit. I had both software

but I can't do a simple projects. So, Please guide me with simple

project with EST and NI VeriStand.

Another problem which I faced in veristand during the accessing of

models which are created in LabVIEW. Also while running the project it

shows some error. So, I need your to go with VeriStand and EST toolkit

Thanks & regards,

suresh