VeriStand FPGA XML Builder Node Feedback

[Ryan_S]

Hey Mathieu,

We appreciate the feedback on accessing the scripted code, and we'll investigate creating snippets from the generated code.

With regards to the packing of FXP inputs of 16 bits or less, it is expected that they would only be packed in pairs as VeriStand accepts items as FXP32 (up 32 bits) and FXP64 (33-64 bits) as is discussed in the VeriStand help.

What isn't expected, however, is for the items entering the join to be 16 bits or less. The code assumes that the wire will be 32-bits or higher coming out of the conversion. So, as you pointed out, this is a bug and could be fixed by adding the U32 conversions. I've added this to our bug list and we hope to investigate it shortly.

--Ryan_S.

[Hissi]

Hey Ryan,

thank you for updating it! It works fine.

But now I have a problem to install it on another computer. There is now only LabView 2014 available and when I try to open the file with the JKI VI Package Manager an error message pops up (This package is not compatible with your operation system or any LabVIEW version installed on your computer). Maybe the compatibility in the package was net refreshed?! Is there a workaround to install the FPGA XML Builder Node?

Thanks,

Arnold

[Hissi]

Problem solved ... I took the old (wrong) version from my hdd.

Thanks!

[Ryan_S]

Hey Mathieu,

We've fixed the FXP bitpacking issue you identified and have uploaded the latest version of the node to the add-ons page (ver 1.1.1). We also added code to the node so that it will now copy its scripted code into a new VI and save it as "VeriStand FPGA XML Scripted Code.vi" in the LabVIEW data directory. In future versions we may add the capability to directly convert the node to its scripted code but we'll need to evaluate that feature. For now, the code is available in the VI that the node will create.

Let us know if you have any other feedback or conerns.

--Ryan_S

[MSteiner]

Fantastic !

You were super fast...

I couldn't test the FXP16, but I can confirm that the code is actually saved in the LabVIEW data folder, which is great since it alloaws us to check AND modify if needed

Thanks a lot

[timtamslam]

Glad we could get you something quickly, Mathieu. Thank you explaining your concern which led to us implementing that. It definitely helped us realize how useful it would be an how much of a pain the tool can present when it doesn't work properly.

Please continue to send in any feedback you have

[joshe]

Hi Ryan,

I hope you can help me. I am not able to get anything to work correctly once I compile my FPGA using this add-on.  I can't get my AO for both current and voltage to work, and my AI (9205) in differential mode reads the same for all the channels.  I don't know if I have something on the FPGA side setup incorrectly or if I am using your add on incorrectly, but I could use some help.  My understanding (which is limited for FPGA) is that the FXP used with the AO in Calibrated mode should use a scale of 1, so all my analog channels are scalled to 1.  I also just started to get an error generated when I made the XML code.  I have attached the project.  Please let me know if you see anything.  Thanks for the support!

[Ryan_S]

Hey Joshe,

At first glance, my guess is your AO isn't working because you haven't configured the Fixed Point Word Length (WL), Integer Word Length (IWL), or Sign for each of your outputs. We default the node to have a WL of 1 and IWL of 0 for new FXP Analog outputs. Unlike inputs to the node, we cannot automatically detect the FXP type of the wire so you must specify it in the node.

This is also discussed in the "Instructions for Use" PDF on the download page for the add-on.

As for the error you're receiving, it's error 1357 which states that "A LabVIEW file from that path already exists in memory, or exists within a project library already in memory". Do you have the VI with the generated code open while also trying to generate new code? If so, I'd expect you to get that error.

Hope that helps!

--Ryan_S

[Ryan_S]

Hey Joshe,

Another thought. As for the duplicate readings from your 9205 AIs, you've got quite a few 9205s in the project/FPGA VI so I'm not sure which one you're talking about (and I didn't see anything jump out at me as incorrectly configured) but I'd start by making sure that the voltage you're applying to the input is being read by the FPGA. The easiest way to do that is to place indicators on the wires in question then recompile the VI and run it interactively while VeriStand also uses it to see what values are being read.

First, you'll need to compile the bitfile into the same location that you're storing the VeriStand FPGA XML file (in order for the next steps to work). Then, add the XML file to your system definition file in VeriStand and deploy. Then go back to the FPGA VI and click run, and it will connect to the FPGA target while VeriStand is running and allow you to see the values on the indicators (without interrupting anything). If the values are correct, then it is something with the node (add-on); if the values aren't correct, then check your wiring.

When you're done troubleshooting, do not stop the FPGA VI, rather just close the front panel. Also, when "running" the FPGA VI do not "connect" to the RT target (from the project, this would actually interrupt VeriStand) but the target in the project does need to be configured with the correct IP address and on the same network as the host computer. For more information about debugging your FPGA VI interactively with NI VeriStand, please contact support. If you determine that the values are making it into the FPGA VI but not up into VeriStand, please let us know.

Hope this helps!

--Ryan_S

[joshe]

Thanks for the direction Ryan.  I will try these out and post an update.