5761 Trigger Leads Analog CH 0 by 10.16 usec

[Denn_Mann]

Hi LV Developers,

I am having a bit of a headache here working with my FlexRIO.  I have a 5761 AC Coupled Digitizer connected to a 7954r FPGA.  All of this is mounted on a PXI Chassis 1031DC and I am running the system remotely through Ethernet.  I am trying to do someting that is very simple: Use the SYNC output of my Agilent 33220A function generator to Trigger the TRIG line of my Digitizer in order to collect the waveform coming out of the function generator for a pre-specified amount of time on Channel 0.  My code searches the TRIG line for a rising edge and once it detects it, it collects "X" amount of samples at a rate of 250 MHz until these "X" samples add up to the pre-specified sampling duration shown as "Record length in microseconds" on the screenshot below.  Everything works well, and I can even get this system to trigger on falling edges.  The problem is that the SYNC line is not in phase with my Output line when I record these.  My Output line from the function generator seems to be leading the Sync line by 10.16 usec.  Ideally, the SYNC lines becomes a TTL high (3.46 V) when the Ouput voltage is greater than zero.

[Denn_Mann]

Here is the screenshot!\

[Denn_Mann]

The lead actually depends on the frequency of the Output signal coming out of the function generator. I have found the following table:

frequency            Output lag in Sample points

5MHz            19 samples (@250Mhz Sample rate)

10MHz            9 samples

20 MHz           5 samples

and this is as high as my function generator can go.  I plan to use this FPGA code to run a 10kHz signal.....so extrapolating the graph, I think I may be several hundred of samples out of phase.