The pins you refer to on the PXI-6052E are part of the local bus feature found on all PXI boards and documented in the PXI Specification.
The local bus feature allows boards to communicate to adjacent boards on the left and right of its slot position (hence LBL 0..12 is local bus left and LBR 0..12 is local bus right). The bus itself is 13 bits wide (don't ask me why!) and generally is used to pass analog signals (up to 42V) between modules without having to actually go onto the PXI bus itself (and therefore avoiding bus bandwidth problems).
The ability to utilise the local bus will be dependent on the hardware manufacturer - the pins have to be there in order to comply with the specification. The specific pins you referred to are not brought out to the I/O
connector so I would question exactly what you thought you might use them for?
The short answer is no they cannot be reconfigured for use by the user (without resorting to register-level programming). The PXI Specification can be downloaded from the PXI System Alliance web site if you are interested in reading further (http://www.pxisa.org) - there is also a good tutorial elsewhere on ni.com:
http://zone.ni.com/devzone/conceptd.nsf/webmain/5895FDE45002985486256BBB0056442F?opendocument&node=1525_US
Jeremy
