FPGA Block Memory and FIFO Timing

[RichieA]

Hello,

I'm trying to access data from block memory and a FIFO, both having an equal number of elements.

The data I'm trying to access must be coordinated with the timing diagram of a Xilinx block I'm using to process the elements from the FIFO and the block memory.

My Xilinx block has a 3 clock cycle offset and a no clock cycle offset, which may lead to my usage of delay nodes.
My question is, does the outputting of an element from a FIFO occur within one clock or a whole clock cycle? Also, I'm aware that there is a clock cycle delay to output
data from block memory to account for the initial read, which will lead to my choosing of the 3 clock cycle offset. It becomes a matter of deciding how many delay nodes to use.

Cheers

[Esteban.R]

Hi RichieA

I will like to ask you some questions in order to understand you question better

Are you using all the block memory and FIFOS on the FPGA? Or do you have any FIFO communicating with the host?

Are you using single cycled timed loops on your application?

Regards

Esteban R.

[RichieA]

Hi Esteban,

All block memory and FIFO blocks are in a single-cycle timed loop in the FPGA.
I'm essentially feeding one set of data at a time from the FIFO and block memory to a Xilinx block.
To be more specific, the Xilinx block is an FFT block. It's configured such that it takes in one datum from the FIFO and one datum from the block memory within one clock cycle.
However, my misunderstanding is with regards to the FIFO and block memory and how long it truly takes to read data and/or output data, i.e. within vs. a full clock cycle.

And yes, once the FFT block is done processing all of the data, the output is of the FFT block is sent to a FIFO that communicates with the host.

Cheers,
Richie

[Esteban.R · Accepted solution]

Hi RichieA

If the function either if it is a FIFO or a block memory is inside of single cycled timed loop then the function and all that is inside should be executed in one tick. Keep in mind that when you compile you are actually programming and connecting a gate array so when the compiler runs it will try to create the FIFO or the memory to be executed on one tick. If this is not possible you should get an error in either LabVIEW or in the compilation process. Here is a links with more information.

Single-Cycle Timed Loop FAQ for the LabVIEW FPGA Module

Regards

Esteban R.