Hi,
I'm trying to derive a 115 MHz clock from the PXI_CLK10 base clock on my 7953R module. The project says that the clock frequency is available and a valid configuration (mulitiplier is 23 and divisor is 2 giving exactly 115 MHz) but I also get a warning saying that the derived clock wil not be phase aligned to the parent clock. Why is this? Also why is it impossible to derive a clock higher than 140 MHz using the PXI_CLK10 as a parent clock?
Thanks,
Nick
