Hello !
I'm using PXIe and FPGA modules (5781 I/O modules + PXIE-7962R FlexRIO and PXIE-1075 chassis) and I'm experiencing some problems related to the ADC...
I've reduced the problem to its simplest form (see attached screenshot) and when recording a DC signal and transferring it to server using FIFO, it appears that some digital glitchs occur (up to 1 every 10 microsecond)... see atached picture for an example...
The problem occurs when using all available FPGA clocks OTHER than IOModuleClock0/IOModuleClock 0 and 1.
However, for my "real" application, I need to decimate the clock (at 20 Mhz and below) and to use triggers, such that none of those clocks can be used (IOModuleClock0/IOModuleClock 0 does not support PXI triggers and IOModuleClock0/IOModuleClock 1 doesn't support clock decimation)...
So 3 solutions could be proposed :
-1. using onboard 40 MHz clock and avoid ADC glitches
-2. using IOModuleClock0/IOModuleClock 0 and enabling PXI triggers
-3. using IOModuleClock0/IOModuleClock 1 and enabling clock downsampling (decimation)
Unfortunately, none of those solutions are possible for now... Could you please help me ?
Here is my software configuration:
- Labview 2010 SP1
- FlexRIO 1.6.0
- Compact RIO 3.6
- FlexRIO Adapter Module Support 2.2.0 (has been updated as suggested here :http://forums.ni.com/t5/LabVIEW/fpga-IO-module-clock-with-TRIG/td-p/1750046)
Thanks in advance !
Best regards
Nicolas
