HP loop count incrementing on adding FPGA device in system definition file in veristand

[SunilLengare]

We have sinusoidal wave generation with FPGA and acquisition of current sensed voltage signal acquisition with FPGA in veristand project.

But we are observing HP loop count incrementing because of addition of FPGA device. we have other hardware such as PXI6363, PXI2510 and also other models but ensured that those are executing properly and those not causing PCL overrun. Can anybody help what must be going wrong with my FPGA in Veristand

[ZYOng]

This question is best to be posted on the VeriStand baord

Adding additional components increases HP count simply indicates that your system is now lacking computational power to process more requests. You can refer to Maximizing System Performance

A few more things you can try:

1. Assign core manually to redistribute the CPU load

2. Reduce PCL rate, or use higher decimations for components that require lower update rates.

3. Use a more expensive PXIe controller with more cores or higher processing speed.

[SunilLengare]

Thank you ZYong, I have posted same in Veristand Board as well. previously I did not find veristand board, but I did found now, I am going through literature you shared. I might come back if any more questions. Thank you so much for replying.