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Implementing IDL streaming for FlexRIO in python API

Hi Terry,

 

I have two cards that I am trying to use: the 5764 digitizer (integrated FPGA) and a 7976R (modular FPGA) + AT1212 pulse generator adapter module.

 

I read that all FlexRIO cards after a certain version are synchronized to the 10 MHz backplane of the chassis.

 

After properly arranging the triggers, I was able to reliably acquire a waveform every trigger, although there is about 300ns of don't care samples before the acquired waveform. I'm assuming its due to delay in my set-up. 

 

The only thing left to get it running at a basic level is a form of handshaking between the two cards. The order of operation is:

1. Pulse generation. PXI line trigger to digitizer

2. Acquire signal. Send acquire finished PXI trigger to pulse generator

3. Repeat X times

 

Currently, this is all implemented with control logic within the FPGA to set the PXI lines HI/LO. Let me know if you have any pointers.

 

Sincerely,

 

Dorino 

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