I am an FPGA engineer, currently new to the LabVIEW FPGA [LV-FPGA] platform. For hands-on practice, I designed a simple D flip-flop VHDL IP and attempted to integrate it with a PXIe-7915 card (installed in a PXIe-1095 chassis) in IP Integration Node [IPIN] mode. The block diagram and VHDL source files are attached below.
The issue I’m facing is as follows:
In my VHDL IP [file: DFF 1.txt], I sample the output data and its corresponding valid signal [Din, Din_valid] from the LVFPGA FIFO module and pass them directly to Dout and Dout_valid, respectively, within a clocked process. While the data [Din] is correctly sampled to Dout on each rising clock edge, the Dout_valid signal remains stuck at ‘LOW’. When I probe the FIFO’s Output Valid signal using an indicator, it behaves correctly — meaning the problem lies in how it’s being sampled within the VHDL process.
Interestingly, if I assign Din_valid to Dout_valid concurrently [file: DFF 2.txt], it works fine. However, if I use an intermediate signal — for example, assign Din_valid to Din_valid_s, and then drive Dout_valid from Din_valid_s — the problem reappears, and Dout_valid remains LOW.
Could you please explain why this happens, and how I can correctly sample both the FIFO output and its valid signal inside a clocked VHDL process?
