Logging using RT-FIFO - inconsistency and zeros logging

[LuizFelipe]

Hello everyone,

I'm trying to make a data acquisition and logging application for a PXI-8133 with PXI-4300 analog voltage input module. After testing different templates, I came up with two loops, a deterministic acquisition, and a low-priority one for logging, communicating using shared variable with RT FIFO enabled.
I need to be able to start and stop logging while VI is running, without interrupting the acquisition and signal plotting.

VI attached is working well for sampling frequency of 1kHz and number of samples of 1000. When I change some of these values, it logs zeros sequences in the output file as if the buffer had been filled without the correct signal. How can I have a VI that accepts different sampling frequencies?

I would like to have a overall feedback on this VI. Is this the best practice or there is better one keeping it simple?

Thanks

[lferreira]

Hi,

Which sampling frequency and sample values  do you set that cause the behavior?

Quickly taking a look at your code, I assume you are using single process shared variable with RT FIFO enabled, but I am not sure whether you set single element or multi-element. Both loops in your code are set up to run in different rates and that may cause data loss because one loop writes faster than another reads. To avoid data loss in a inter-process deterministic communication  I recommend you to use a buffered and real-time communication mechanism such as RF FIFO functions. They are ideal to stream data from a Timed Loop to a log data loop.

For more details about Real-time communications, take a look at:

Understanding Communication Options Between the Windows HMI, RT Processor, and FPGA

Regards,

[LuizFelipe]

Hi, thanks for the reply.

I am using Single Process shared variable, with RT-FIFO multi-element enabled. I tried attaching the .lvlib file but it is not allowed.
Doen't using shared variable with RT-FIFO enabled already replaces the need of using FIFO functions?

At the moment my program is experiencing loss of data during the duration of the buffer size window, as attached figure. Increasing the size of the FIFO only postpones the problem, how do I avoid this data loss? I'm using the two loops with the same rate (10ms)