Minimum simulation step size for the PXIe 8881 Linux RT Real-Time Simulator

[chychy123]

Hello everyone, what is the minimum simulation step size of the PXIe 8881 Linux RT real-time simulator? I need to simplify the model to meet the requirements of real-time simulation.

[ZYOng]

I guess you are trying to compile a Simulink model to run on a PXI Linux RT controller? 

It depends on how complex your model is. For a very simple addition operation, you might be able to run at microseconds level.

[chychy123]

Thank you very much, I used AMESIm to build a real-time model, the model is more complex, there are 12 valve regulated cylinder models. At present, in AMESim, the fixed step simulation time is set to 0.0001s, which can be simulated. However, it is not certain whether it will run on a real-time target.

[ZYOng]

It depends on many factors. The only way to know is to run the model on an actual RT target. If you have other tasks running at the same time, for example, multiple models or hardware I/O, it might consume the CPU resource and reduce the performance as well.

[nsprateep]

Dear sir,
we are selected PXIe-8881 processor and selected other interphase are Analog input PXIe-4302 and extinction TB-4302C One set, Analog Output PXIe-6738 three cards, Digital input PXIe-6529 one card and Digital output PXIe-6513 three cards.
And still searching for ARINC825(2 Channels), ARINIC 429 (8 channels), RS422(18 Channels), TSN Ethernet (6 ports) and Ethernet (4 Ports).

For these boards interphaseing we need back plain, please suggest back plain part numbers.
If you want give suggestions please suggest and encourage us please.