NI 5751 Clk 10 MHz Sync

[thom_j]

Hi

I'm pretty new to Labview and FPGA programming. In my project, I would like to synchronise the ADC of the NI5751 to an external frequency normal supplied by the "10 Mhz Ref In" of a PXIe-1075 chassis. Is there any way that the 50MHz sampling frequency of the NI5751 is steered through the 10MHz? And additionally, is the "PXI Clk10 MHz" which can be included at the FPGA project as base clock derived from that "10 Mhz Ref In"?

Thanks.

Regards,

Thomas

[Marco_Brauner]

Hi Thomas,

in order to synchronize the ADC on your FlexRIO-adapter-module (FAM) to the 10 or 100 MHz PXI/PIXe-Clocks, you need an additional PXI/PXIe-Timing card (i.e. PXIe-6674T) which can be

synced to an external RefClock or the chassis-Ref-clock and then provides a synchronous sampleclock-signal which can be used with the 5751 CLK IN. 

regards

Marco Bauner NIG

[thom_j]

Hi Marco

Thanks' for the answer.

We got a NI-6674T module, so no problem to create a DDS with 50MHz and having it synchronized with the 10MHz. I just wonder, you mean, I should connect the ClkOut from the NI-6674T (with 50MHz output) to the ClkIn of the NI-5751 module, right? Is there also a way to use an internal connection via DStarA?

Regards,

Thomas

[Marco_Brauner]

Hi Thomas, you´re right. I was not quite sure if we connect DSTAR-Lines to the FAMs.

see http://digital.ni.com/public.nsf/allkb/AF9EFD4A8CB9F7748625774C0055A657?OpenDocument

regards

Marco Brauner NIG

[thom_j]

Hi Marco

Ok, thanks'. Now the next questions :-). I'm not sure how to setup the DStarA line. I can generate a DDS with the 50MHz at the NI-6674T, but I don't know how to route this. In the manual of the NI-6674T, I found several lines for the DStarA, named as DStarA0..DStarA15. Are these the same as the DStarA which is to be set for the NI-5751? Additionally, if I want to use the DStarA line for the ADC, do I need to use the standard driver for the NI-5751 or the multiple device driver?

Thanks'

Regards,

Thomas

[thom_j]

Hi Marco

Just to check. In general, I could use the ClkOut from the NI-6674T to provide a synchronized 50MHz signal and use the ClkIn of the NI-5751 to synchronize the ADC. The problem, I see is that the ClkOut of the NI-6674T is AC coupled with a "5Vpp into high Z" but the ClkIn of the NI-5751 (input is >50k Ohm) is expecting a logical signal with Vlow=0.6V and Vhigh=2.2V with maximum ratings of -0.5V to 3.5V according to the manual. Therefore, please correct me, this could destroy the hardware, right? So, I guess, the only way is to use the DStarA connection, right?

Regards,

Thomas

[Marco_Brauner · Accepted solution]

Hi Thomas,

yes you´re right it´s 3.3V at the CLKIN of the 5751. Anyway, go for the DSTARA- approach.

In the User Manual of your PXIe-10xx chassis you will find a section called "System Timing Slot"

in the Getting Started chapter which is giving you the routing of DSTARA to the slots of the chassis.

For example PXIe-1082:

cheers

Marco

[thom_j]

Hi Marco

Thanks', this worked. What I did now is to synchronise the external 10MHz frequency normal with the internal PXI_10MHz via the NI-6674T card. Then I created a DDS (which is based on the PXI_10MHz as it seemed) with 50MHz and routed it to the PXIe_DStar9. The timing card is in place 10 of the PXIe-1075 chassis and the FPGA NI-7966R in place 11, therefore according to the manual of the PXIe-1075 p. 1-9, I used the PXIe_DStar9 line. In the labview project, I set the IoModSyncClock to PXIe_DStarA in the properties of the IO Module. Then, in the FPGA VI, I set the "IO Module\Sample Clock Select" to 1. I was not using a forced reinitialisation here as it seemed to be working. Do I miss something? Otherwise thank's a lot.

Regards,

Thomas

[Marco_Brauner]

Hi Thomas,

no I guess that´s pretty much it. Your welcome!

regards

Marco