NI 6585 IO Clock Module 0/1 and Timed Loop

[BillMe]

I have an external LVDS signal (clock) coming in to a 6585 and want to acquire data based on that signal, so I will connect it to the Global Clk input and choose "IO Clock Module 0" as the source for my timed loop. However, I only want the timed loop to trigger on the falling edge of the clock. Is that configurable?

And is access to falling and rising edges only available with the DDR connector CLIP? My interface is a 3 wire (clk, data, enable) serial so I'm using the Basic Channel CLIP to get access to just the wires I want but then I lose the falling/rising edge I/O property.

[David-A]

Its configurable in the sense that you can create a custom CLIP for the 6585 that does what you're asking. However the path of least resistance is to use the DDR CLIP that ships with the 6585 and discard the data that arrives on the rising edge.

[BillMe]

I stayed with the Basic Channel CLIP since I want access to individual data lines. I borrowed the "edge trigger" circuit in an example to look for the falling edge of one of the lines (clock from UUT) and then save the data. Turns out I don't need to concern myself much with the IO Module clocking as long as the sample clock rate is at least several times my data line clock freq. Thanks.