Hello everyone,
hope someone experienced can help me.
I'm generating a train of RF pulses (external source).
All the pulses are with the same amplitude, frequency and the same phase.
I sample these pulses with NI PXIe - 5764 digitizer.
The external source provides a trigger for each pulse and 10MHz clock.
I routed the trigger and 10MHz clock of the source to the PXI backplane DSTARB and PXIe 10MHz using NI PXIe 6674T timing card (with PLL).
I'm using DSTARB backplane trigger as the trigger source for the digitizer.
I'm using the PXIe 10MHz as the reference clock for the digitizer sample clock (I defined it
in the host using flexrio properties node - see attached picture).
The problem - the phase is changing linearly from pulse to pulse which seem to be a synchronization issue
between the sample clock of the digitizer to the 10MHz of the source.
question - are the flexrio properties defenitions I add to the HOST (attached) are the right ones?
what could be the cause for the phase skew from pulse to pulse and how I can solve it?
Does TCLK can help to this issue?
BR
Ofir
