PXIE-6570 Channel timing

[svl123]

Hello,

I would like to know what is the minimum timing that is achievable between digital output channels on the PXIE6570. I know that the device has a maximum vector frequency of 100Mhz but then the Specifications document also mentions that the "Minimum required edge separation" is 5ns. Does this mean that two channels can burst the same pattern with one lagging the other by 5ns?

Thank you,
svl123

[sherlockholm]

Hi svl123,

What exactly are you trying to achieve?

You can burst the channels at the same time. You can also modify the Drive Data in your timing if you want something to have an offset. Is this what you are wondering?

When you are talking about the Minimum required edge separation, this is referring to time required between the "driving" events. In most cases, you would just worry about Drive Data and Drive Return, unless you are using the SBC format. I would refer to the timing help for more information:

Timing

[svl123]

sherlockholm,

I want to know if it is possible to get time resolution finer than 10ns. I know that I can offset a channel by modifying the vector itself but in that case I am still limited by the 10ns resolution. I guess my confusion comes from not really understanding what "Drive data" parameter does in the Digital Pattern Editor. From the description of the "Drive Data" field it appears that if I enter, for example, 5ns into the Drive Data field for some pins then those pins will get data driven to them with a 5ns offset and thus the entire pattern will be offset by 5ns. Is this not how it works?

Thank you,

svl123