PXIe-6358 timing info

[tara.fab]

I would like to know :

• which timing aspects shall be respected with sampling clock mapped on PFI inputs with respect to signals sampled on other PFI inputs or Port 0 inputs (setup, hold timing parameters) and
• the delay + jitter between the front edge of the PFI inputs (sampling clock) and the sampling of analog inputs located on the same 6358 board of the PFI sampling clock or on others 6358 boards (PXI chassis : PXIe-1082) .

I have checked the user manual (DAQ X Series, 370784G-01) but no such information.

Best regards

[RobGeografo]

Hi,

Essentially, if the synchronization requirements are so high that these aspects (setup and hold times) are been considered it is likely that synchronizing through this method is not even an appropriate option to consider, and that much more precise methods would be necessary, such as using our timing modules. 

As a multi-function module, the PXIe-6358 offers the ability to conduct different measurements within the same card. Although this card has high timing specifications, it is not tailored specifically for high timing and synchronization operations. If this is the requirement, than something in the timing card family may be ideal for the purpose.

Best regards