PXIe-6570/6571 Digital Pattern: how to cycle through more addresses than can fit in the Source memory?

[MichaelT83]

Hello everyone,

I'm using the PXIe-6570/6571 to test a CMOS vehicle, and I need to cycle through > Gbit addresses (each address is 32 bits long). Since the 6570 does not have an APG, I need to generate all the addresses in a NumPy array, which is then load the "waveform" onto the 6570.

The problem is that the Source memory does not allow me to load the entire address list so I'd like to use loops to automatically generate them. And the Digital Pattern editor does not allow variable incrementing, somehow. One workaround that I can think of is to truncate e.g. the last byte of each address, and to generate multiple repeats of the pattern in python, where each repeat has its last byte hardcoded before compiling. That's really sub-efficient.

Is there a smarter way to solve the Source memory limitation issue? I'd love to be able to source multiple waveforms that would be incremented in separate intricated loops but it doesn't look like it's possible.

Any help is greatly appreciated.

Thanks,

Michael

[santo_13]

Is there a reason this can't be a flat pattern if you already know the addresses you need to test? Is it so large that it results in an out-of-memory error?

[MichaelT83]

Hi Santosh,

You're right, my address space is larger than the source memory of the 6570.

I'm trying to figure out whether I need to buy a proper ATE (Advantest, Magnum..) or if I can continue using the PXI system - which is very flexible so nice to debug.

Thanks,

Michael

[santo_13]

Michael, I recommend generating a flat pattern will all the addresses included instead of going with on-the-fly data in source memory.

If you're not aware, you can write the pattern as txt file (digipatsrc) and compile it into digipat

Text Pattern File Syntax - NI