PXIe slot sampling rate limit

[Stopreal_tw]

Our lab uses PXIe-8880 controller as well as PXIe-1075 chassis. Previously, we plug PXIe-7972R(FPGA slot), NI 5734 (FlexRIO module) into the chassis to synchronizely use 32 ai channel input the 16-bit data in 8MHz sampling rate. After the FPGA, the data would be averged by 8 and the data would be 8-bit each channel (one slot has 4-channel, which would form 32-bit data). The program could run but would lose data in few seconds.

Recently, we want to reduce the sampling rate with PXIe-6368 or PXIe-6386 ai channels. However, in the simulation part, the program reports error when acquire 32 ai channel data by 1.5MHz sampling rate (The program uses normal daqmx function).

If the dataflow is too high, I wonder why previously we could run the program with NI-5734 and PXIe-7972R with even higher sampling rate? Is the buffer between PXIe Slot and labview program the same? Whether there are better method to conduct data acquisition with higher sampling rate with 6368 or 6386?

[ZYOng]

See Error -200279: Unable to Keep Up With Acquisition in NI-DAQmx

In short, call DAQmx Read VI more frequently or read more data points per read.

[Stopreal_tw]

I think it's more likely to be the speed limit. For the requirement of experiment, the sampling rate to be over 2MHz with 32 ai channel, also, the sampling should be continuous for at least 10 second. The problem still occur when I reduce the number of samples per loop. My question is that why NI module + FPGA module could tolerate higher dataflow but PXIe (DAQmx module) cannot. Also, is it possible to connect PXIe-6368 or PXIe-6386 with FPGA module?

[santo_13]

Without looking at the exact code, we couldn't comment why it was working. Both FPGA and 6368 use the same PXIe bus and limited by the system bandwidth (some are slot dependent).