Read without emptying FIFO

[LucG]

Good morning everyone,

My question might simply be a lack of basic knowledge. So forgive me if it looks dumb, but I guess this forum is still the right place to ask. 😉

So! I am using a PXI device to do some data post-processing after image acquisitions. The post-processing itself is actually done on an FPGA. So I need to transfer data between the host and the FPGA. That is not a problem in itself. I managed to develop simple VIs using FIFOs. The problem for me is that when the FPGA reads a FIFO, it takes the element out of the FIFO. So if I want to use the sample again, I have to right it one more time in the FIFO from the host. That is something I would like to avoid. Let me explain a bit what kind of post-processing I need to do...

I start with a set of images stored in an AVI file.

The processing I need to do involves four successive images: im1, im2, im3, im4.

So for the first four images of the AVI file (im1, im2, im3, im4), the operation is simple: write images in the four respective FIFOs, process on the FPGA, and get the result back on the host.

But the next post-processing step now involves im2, im3, im4, and im5. Only one image changed: im1 in replaced by im5. The three others are axactly the same as what we used previously. Unfortunately, all the FIFOs are now empty! So in practive, I need to write the four images again. In order to save time, it would be better to simply write im5 where im1 was stored (therefore erasing im1 at the same time), and start the pressing again on the FPGA (im2, im3, and im4 beeing still in memory).

So here is my question:

What kind of data transfer tool can I use between host and FPGA, so that only the host can erase data in memory, and so that when the FPGA reads the data it actually just "reads" and not delete the sample at the same time?

Thanks a lot for your answers.

Best regards.

Luc

P.S.: if it has any importance, here are the devices I am using.

PXIe-1071

Controler PXIe-8133

FPGA  PXIe-7962R

[crossrulz]

I don't understand why you don't just write the one image to the FPGA, the one that needs processed.  No need to process the same images again.

[LucG]

Well... Correct me if I'm wrong, but reading a FIFO empties the FIFO, right?

So if I want to read im2 on both the first and the second iteration of the post-processing, I have to write it two times in the FIFO. Is that correct?

[LucG]

In case I was not clear enough in my first post, here is some more information...

The processing I need to do invloves four successive images. I need the four images. If the FPGA can read only one image, no processing can be done!

The operation beeing done is basically putting the four images (pixel by pixel) through a 4x4 matrix and getting four images in return. Let me try to write down the mathematical operation. For the following, keep in mind that saving the results Ra, Rb, Rc, and Rd is not a problem. I consider images are saved properly. My concern is just to transfer the input images 'im' without writing all four images to the FIFOs each time (if that is ever technically possible...).

----------
Process of im1, im2, im3, im4 for a given pixel (x,y) :
Matrix . [im1(x,y); im2(x,y); im3(x,y); im4(x,y)] = [Ra(x,y); Rb(x,y); Rc(x,y); Rd(x,y)]

Process of im5, im2, im3, im4 for a given pixel (x,y) :
Matrix . [im5(x,y); im2(x,y); im3(x,y); im4(x,y)] = [Ra(x,y); Rb(x,y); Rc(x,y); Rd(x,y)]

Process of im5, im6, im3, im4 for a given pixel (x,y) :
Matrix . [im5(x,y); im6(x,y); im3(x,y); im4(x,y)] = [Ra(x,y); Rb(x,y); Rc(x,y); Rd(x,y)]

Process of im5, im6, im7, im4 for a given pixel (x,y) :
Matrix . [im5(x,y); im6(x,y); im7(x,y); im4(x,y)] = [Ra(x,y); Rb(x,y); Rc(x,y); Rd(x,y)]

Process of im5, im6, im7, im8 for a given pixel (x,y) :
Matrix . [im5(x,y); im6(x,y); im7(x,y); im8(x,y)] = [Ra(x,y); Rb(x,y); Rc(x,y); Rd(x,y)]
----------

As you can see, there is only one single frame that needs to be refreshed from one process to another.
So is there a way to refresh this frame, without writing the three others again in the FIFOs?

Thanks for the time you spend helping me crossrulz.
Luc

P.S.: I am talking about FIFO all the time, but if the right way to do it would involve using something else like block memories or whatever, just say it. I am open to any suggestions. 🙂

[crossrulz]

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@LucG wrote:

Well... Correct me if I'm wrong, but reading a FIFO empties the FIFO, right?

So if I want to read im2 on both the first and the second iteration of the post-processing, I have to write it two times in the FIFO. Is that correct?

---

Why do you need to process im2 again?  If you don't need to process that image again, then don't send it down.  You already have the result.

EDIT:  Alright, just saw your third post.  You could save the image data in a memory location on the FPGA and just have the FPGA use that data if there is nothing in the FIFO.

[LucG]

OK.

Let me have a look at that...  😉

I'll come back to you later.

Thanks for you help.

Luc