Hello!
I am working in my thesis, and I am really stuck I hope someone can give me a clue!
I need to build a repeater that delays UMTS BS signals and then repeat it with a variable delay from 0ms to 10 ms (20 MHz BW). I am ok if I can repeat the signal comming from one BS (5 MHz BW). Rigth now I am not able to repeat signals with a BW higher than 1 M.
I am using just the NI PXie 5641R (later on I will also use a downconverter and a upconverter). I am working with a host API. What I am doing is the following:
1) Read groups of samples from the ADC as fast as possible (in a while loop without delay)
2) Put the samples in a queue
3) Delay the DAC 10 ms, so it start after the ADC has kept some samples in the queue
4) Read samples from the queue and sent it to the ADC (I guess I am sendint it to the FPGA buffer). If there is no samples at the queue the host waits until there is a group os samples.
I am using a chunk of samples of 10k or 100k (the size of the group of samples I am reading and putting in the queue), I know this value should not be to small or to big (in order to increase speed).
Up to 1 M using 10K the system seems to work correctly. At the beggining the queue grows until the DAC starts working and then the elements in the queue are taken as soon as they are being queued, so there are no elements in the queue.
When I increase the sampling frequency (higher than 1 M) the queue grows even when the DAC is workig (in fact I dont know why I am not getting an underflow error since my DAC and ADC rates are the same, how can I have the same rates and be able to keep samples in a queue??). If I increase the chunk size I get an error time out in the DAC, it seems that the samples are not transmitted fast enougth to the DAC.
Do you think I am doing something wrong, or it is the maximium rate my system can stand?? Do you think there is a way to improve the system?
I am basing my desing in http://zone.ni.com/devzone/cda/epd/p/id/6193, In the example streaming is done but in the example it is NOT neccesary to abort the session to continue writing, using the 5641 and streaming I need to abort the sesion write and then continue the execution. Is there is a way to repeat an incomming signal without aborting the session (using just the 5641)??
I am open to use async FPGA code, but in this case I am having other problems:
-using feedback node (vi component) with a delay of 100000, the system is not able to compile (out of memory after working 10 hours) . My controller (NI Pxie 8108) has 4G in ram memory
-using Discrete Delay Function (vi component) , this compenent is implemented as a Lookup table (so it is not implemented in the RAM), the delay I want is to big to be handle by the FPGA (it is not able to compile becouse my desing doesnt fit in the device)
-maybe I could use a FIFO but in this case a dont see any way to control a variable delay (i guess the fifo is implemented in the FPGA RAM). the VI FIFO doesnt allow to chose element.
Any suggestion? HELP!!!
Regards
Carlos J Rueda
