Hello guys.
I am implementing a communication system with PXIe-7965 / NI-5791.
The problem is element to read from FIFO.
When I set 2048 BRAM as an input FIFO, it cause an overflow (not always but blinking) (the number of element to read : 2048~2053).
But input data is continous stream, and IFFT start to read after 1+ 3 clock additional delay.
So I increase the number of element as 5012 then the number of element is only 5. I think it cannot write into FIFO correctly.
Through computer development simulation, it works not only algoritms but also output values.
However, after compliation PXI cause above problems.
I aleady searched posting relate to FIFOs
https://www.ni.com/docs/en-US/bundle/labview-fpga-module/page/choosing-between-the-fifo-implementati...
http://digital.ni.com/public.nsf/allkb/5338E45E161D74CE86256FAF0056FD84
But I cannot solve this issues.
If someone meet same problem or has been solved, feel free to advice me.
Thank you
Best Regards,
Hyunwoo.
FYI
System parameters
104 MHz SCTL
Control Elements to start reading IFFT : 2048 (at the attached figure)
All FIFOs : Slice Fabric
Compliation summary as
Compilation completed successfully.
Device Utilization
---------------------------
Total Slices: 64.2% (9452 out of 14720)
Slice Registers: 40.0% (23526 out of 58880)
Slice LUTs: 36.0% (21174 out of 58880)
DSP48s: 14.1% (90 out of 640)
Block RAMs: 23.4% (57 out of 244)
Timing
---------------------------
40 MHz Onboard Clock: 40.00 MHz (71.96 MHz maximum)
200 MHz Clock: 200.00 MHz (266.95 MHz maximum)
104MHz: 104.00 MHz (104.78 MHz maximum)
TS_SampleClk: 250.00 MHz (maximum)
TS_BusClk: 127.58 MHz (maximum)
TS_SlowBusClk: 131.13 MHz (maximum)
TS_DramClkDiv100: 450.25 MHz (maximum)
TS_IoRxClock: 333.33 MHz (maximum)
TS_Puma20Window_theCLIPs_IO_Module_CLIP0_Ni5791FixedLogicx_McLarenPll130x_SampleClkPllOut: 136.95 MHz (maximum)
TS_Puma20Window_theCLIPs_IO_Module_CLIP0_Ni5791FixedLogicx_McLarenPll130x_SampleClk90PllOut: 416.67 MHz (maximum)
TS_Puma20Window_theCLIPs_IO_Module_CLIP0_Ni5791FixedLogicx_McLarenPll130x_SampleClk2xPllOut: 262.26 MHz (maximum)
TS_ClockGenXilinxV5x_TxDcm_TxHighSpeedClkDcm: 272.55 MHz (maximum)
TS_ClockGenXilinxV5x_RxDcm_RxHighSpeedClkDcm: 450.25 MHz (maximum)
TS_ClockGenXilinxV5x_RxDcm_RxLowSpeedClkDcm: 163.21 MHz (maximum)
