Why PCI-7831R has 15us delay between analoge input and analoge output ?

[labview fpga]

I am using the FPGA in design a high speed PID controller.
I suppy a source signal to the 8 channel AD In and read the signal simultanious in FPGA and send it to analoge output.
There is a 15us delay between the source signal and AO signal.

In the fpga i used 2 while loop, one for AI. The cycle time for this block is around 4.3us.
In the mean while, another while used to send the read AI signal to AO. I used local variable to
transfer the data between 2 while loops. For the AO while loop, i fix the loop time to 5us.
After remove the AI cycle time which is 4.3us, i still have about 10us delay.

My question is, where is this 10us come from?
Could it be reduce?

Thanks!

W.F Cheng

[GValdes]

Hi, W.F Cheng

Ideally, the convert rate for the AI in the 7831R is 4 us, and the update time for the AO is 1 us. Also, based on the architecture of the VI, extra jitter could be introduced if you are trying to access shared resources (like local variables) at the exact same time. Those could be some of the reasons why you are getting a delay in your application. Feel free to attach a simplified version of your code, so we could see if there are ways to improve the code.

Regards,

GValdes