data clock x2 in FlexRIO 5764?

[jiangliang]

Hi there

I want to do some raw data processing in 5764 at 250MHz, but the data clock is running at 125MHz, I was wondering what kind of data will I get if I want to read AI 0 Data N-x?

Will this system update all channels at 125MHz even if I'm reading at 250MHz or update half channels at 250MHz? If they do update at 250MHz, where can I found some details about how it works?

Thanks!

[Terry_ALE]

Check the shipping example for the 5764.

The 5764 samples data at 1 Gigasample/sec per channel.  The data clock rate is 125 MHz which means that each cycle gives you 8 samples from each channel.

The data clock x2 is provided because some DSP needs a x1 clock and x2 clock.

[jiangliang]

Thanks for your reply, by the way, your book on LVFPGA provides really useful insights, I love it very much!

Back to the problem, I did check the shipping example, but not only I couldn't found useful info on how the 8 elements are updated (update 4 elements on each 250MHz clock? if so which order do them update; or update 8 elements every two ticks on 250MHz? if that is the case, which tick do these data update?). I also found it hard to understand, the shipping 5764 example host VI simply doesn't even call the FPGA bitfile, if I did tweak the default FPGA, and compiled it, I can not see any difference with shipping host VI, I don't understand how that comes...

[Terry_ALE]

Thank you for the kind words about the book.

In the shipping example's FPGA code the \instr.lib\FlexRIO\API\FPGA\v1\IO\NI5764\5764 AI Channels.vi VI is being called.  This shows how 8 samples are being read per clock cycle.

Acquisition is run at the data clock rate, not at the data clock x2 rate.