fpga

[mahmoud12]

HELLO everyone,

How do we add more than one VHDL file using CLIP in an FPGA Application ???

in my case, I have 4 files is written in VHDL , so I want to add them using CLIP ????

[Zody]

Did you try to generate xml file for each one of them vhdl file?

You can download the xml generator from here http://zone.ni.com/devzone/cda/epd/p/id/6068

Also, you can discover more about CLIP here http://www.ni.com/white-paper/7444/en

Kind regards,

Ion R.

[mahmoud12]

Let me to descibe my problem :

when I try to check syntax of my VHDL file , an error occured durnig the check 

"Extracting top-level synthesis file information. Please wait...
The following port in the top-level synthesis entity has a type that is not supported. The supported port types are "std_logic" and "std_logic_vector".

Port name: Datain
Port type: STD_2D1(0 TO M-1, 0 TO N-1)

Fix the above error and check syntax again.

"

because I have another VHDL file and in this file I did my library when I create my specific array

"
TYPE STD_2D IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC_VECTOR(11 DOWNTO 0);

"

and this array is my input for my system

[Zody]

Let me see if I undetand correctly.

You have two VHDL files. Your first question was if it is possible to have multiple files used in FPGA. Yes, you have to define xml file for each one of them and than you can use.

The error that you get for the syntax, at what stept do you get it? In what environment is done the syntax checking?

Kind regards,

Ion R.

[mahmoud12]

when I checked the synthax, I used this method:

first, i created my VHDL file

then I created my project labview fpga

and I put  my VHDl in the project labview fpga

then I used this method :

1. Right-click the FPGA target in the Project Explorer window and select Properties from the shortcut menu.
2. On the Component-Level IP page of the FPGA Target Properties dialog box, click the Create File button.
3. On the Name and Source page of the CLIP wizard, click the Add Synthesis File button.
4. Select DemoClipAdder.vhd and click the OK button to add the file.
5. (Optional) Select DemoClipAdder.ucf and click the OK button to add the file.
6. Click the Next button.
7. Follow the instructions in the rest of the CLIP wizard to finish creating the declaration XML file.

   Tip Click the Help button on each page of the wizard for more information about the available options.

8. Click the Finish button to complete the configuration and create the declaration XML file.

The CLIP wizard automatically adds the CLIP to the project.

[Zody]

Hello,

And after following those setps you get the error?

Because your post was about multiple files, right now it seems the error is more in VHDL code rather in LabVIEW integration of it.

Kind regards,

Ion R.

[mahmoud12]

so if it is possible to have multiple file , what is the complete method and all the steps to implement my code ??

notice that in my code I created a library using the package so in labview do i use a package ??