Hello,
I am using PXIe 7966R with 5761 adapter module. The range of frequency for the sample clock in 5761 is specified as 175MHz-250MHz.
I want the sampling rate to be 1MHz. How to do this?
Also in FPGA derived clock option, the lowest frequency which we can generate is 2.5 MHz. I want 1 MHz clock for my operations.
How to generate clock for the frequencies lower than 2.5 MHz?
Waiting for the reply.
Regards,
Aalhad
