Use state-of-the-art high-level synthesis (HLS) technology from Xilinx to create resource- and timing-optimized field-programmable gate array (FPGA) IP without relying on advanced LabVIEW FPGA optimization concepts. This means you can concentrate on the high-level design of your algorithm, quickly explore design trade-offs, and reuse IP to meet new design requirements.
Alejandro Asenjo, and Ellen Zhang, National Instruments
