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Data Reduction and Analysis Using RIO and FPGA

ID: TS6403

Abstract: Some test applications contain high channel counts and high sample rates, so saving all the data and postprocessing for analysis is not practical. Learn how the use of an FPGA to preprocess the digitized input waveforms can greatly reduce the analysis time and storage requirements necessary to determine product acceptability.

Speakers:

Ryan Smith, CertTech, LLC, Senior Staff Engineer

Alan VanDeusen, CertTech, LLC, Director of Systems

Contributors