ID: TS7457
Abstract: As system on a chip (SOC) technology grows more complex and suitable for wearable devices, the current trend is to integrate RF transceivers into SOCs on the same chip to reduce bill of materials cost and area for small form factors. The number of SOC test points is limited to mainly RF and digital inputs/outputs because RF, analog, mixed-signal, and digital building blocks are all integrated. Hence, comprehending the entire SOC functionality and performance increases validation time. At this session, learn how to probe key test points with test equipment and increase test coverage using efficient test vectors from presilicon to postsilicon environments.
Speaker: Satoshi Suzuki, Intel Corporation, R&D Test Engineer
