Comparison of Multisim vs. LV FPGA Real-Time HIL Simulation Results

[BMac]

For the IEEE webcast next Thursday, it was suggested that we do a comparison of the LV FPGA state-space HIL simulation model. In this case, I went through the exercise for a three phase inverter- comparing our LV FPGA state-space real-time simulation (fixed point) versus the Multisim cosimulation results. Here is the results so far and some questions we are asking...

Summary

- In a nutshell, the convergence is very good.

- One question: For some reason the load voltages have about a 500 us lead in the FPGA based model compared to Multisim. Does anyone have thoughts on why that could be? To me it looks like it's just the differences in how the two different solvers initialize?

Multisim schematic:

Cosimulation results compared to LV FPGA HIL simulation subVI:

Notes:

• The inputs to the LV FPGA simulation subVI are the unfiltered output voltages of the inverter (Vab_i, Vbc_i, Vca_i)
• The Multisim voltage waveforms have about a 500 us delay relative to the LV FPGA voltage waveforms.
• The current waveforms show no delay.
• Compared to the paper on which the state-space model is based (link), I had to invert the sign of the Conversion matrix to transform line-to-line currents [iiAB iiBC iiCA] to line-to-neutral currents [iiA iiB iiC]. Why is that? Mistake in the paper?

You can see the constant voltage phase offset more clearly here:

Notes:

• The unfiltered output voltages of the inverter (Vab_i, Vbc_i, Vca_i) from Multisim include the resistance losses in the transistors, so the values are 0.5 to 1 volt lower than the perfect switch model. The probes below show a comparison of Vab_i in on and off states between perfect switch (top) and Multisim switch (bottom).

By comparison, here are the results with perfect switches- the pole voltages are either +Vdc/2 or -Vdc/2, depending on the switch states, which ends up being +/- 400 V line-to-line. You can see the amplitude of the FPGA simulation is slightly higher than Multisim.

Block diagram:

- For these tests the FPGA simulation is executing with a 1 us dT (1 MHz). The LV FPGA state-space solver code can actually run in the FPGA in 28 ticks of a 100 MHz clock, or 280 ns (3.571 MHz) on a NI FlexRIO or PXI-7965R FPGA board.

Comparing simulations for the three-phase inverter circuit with different component values:

- I went in and modified the FPGA based solver so you can load in the A and B matrices during run-time for desktop simulation. (When it's running on the FPGA, you change the matrix coefficients by writing to the FPGA RAM.

- These component values are close to the SEMIKRON six-pack inverter in our demonstration wall.

- Interestingly, the phase shift is less, and almost goes away (the FXPT voltage still leads slightly after 2 cycles if you zoom in).

Startup behavior in first half cycle:

Multisim schematic: