11-03-2011
11:23 AM
- last edited on
05-09-2024
03:47 PM
by
Content Cleaner
Released and orderable for high volume OEM production. To learn more, download the attached factsheet PDF and visit the following pages:
NI Single-Board RIO General Purpose Inverter Controller
Development Toolchain
Open Source IP, Designs and Examples (ni.com/powerdev)
With the NI Single-Board RIO GPIC, you can bring grid-tied power electronic systems to market with significantly lower cost and risk. The FPGA-based system is designed to meet the cost, I/O, and performance needs of most high-volume commercial power electronics control applications, including DC-to-AC, AC-to-DC, DC-to-DC, and AC-to-AC converters for smart-grid flexible AC transmission systems (FACTS), renewable energy generation, energy storage, and variable speed drive applications. Learn more...
January 25, 2016: Update for sbRIO-9607 Zynq-7020 GPIC specifications.
August 4, 2012: Updated for release specifications.
April 29, 2012: Updated for rev. B specifications. This is the pre-production design specification.
February 3, 2012: Functional rev. A GPIC PCBs are in house and undergoing testing and validation by NI R&D.
December 12, 2011: Development project is now officially kicked off. The updated preliminary datasheet document includes the following changes that match the kick-off specifications:
NI would like to say thank you to all the customers that have given feedback on the features and specifications for this product development and we all look forward to the release.
02-09-2012 02:31 AM
Dear BMac,
Could you comment on the following specs from the datasheet, please.
High Speed Digital Output section: it says that 10ns rise/fall time, but where the limitation on the 500ns minimal pulse width comes from? I would expect to be able to toggle the output with 20MHz at least (from the rise/fall timing).
Similar specifications are on the NI 5751 FlexRIO adapter module: rise/fall 10ns, max toggle frequency 1MHz. It is slightly inconsistent in my oppinion.
Thanks
02-16-2012 11:35 AM
Hi Ceslav,
Sorry for the slow response; it's been hectic.
First, consider using a different type of I/O for your application. If you need > 20 MHz speed digital outputs, please use the FPGA Expansion I/O connector (J2). This is a 34-pin, 0.1” ribbon cable connector that gives you 16 unbuffered 3.3 V digital I/O lines (bi-directional) from the Spartan-6 FPGA. Since these are raw, unbuffered and unprotected FPGA IOB signals, you can achieve the maximum speed of the FPGA. The base clock of the Spartan-6 LX 45 is 40 MHz, but you can create derived clocks at faster rates such as 200 MHz. Then create a Single Cycle Timed Loop (SCTL) in LabVIEW FPGA, time it with your derived clock, and place your digital I/O nodes for the expansion I/O signals in the SCTL. Keep in mind that the impedance of ribbon cables is typically 100 Ohms, so you need to consider the length of the cable and termination at the receiving end of the signal. On your receiving board, use traces that have 55 Ohm impedance so that it is matched for best signal integrity. Then you can achieve rise/fall times in the range of a few nanoseconds. Also, you need to be very careful when using the Expansion I/O signals since they are raw, unbuffered, unprotected FPGA input/output buffer (IOB) lines. But for speed, they cannot be beat. Typical uses for the expansion I/O include gate command signals for high frequency MOSFET (and SiC) DC-to-DC converters (switching frequencies > 100 kHz), FPGA-to-FPGA communication, fiber optic transceivers, SPI/I2C sensor interfaces, GPS signals, etc.
Coming back to the high speed digital outputs now… The 12 High Speed DO (HSDO) section outputs are designed to provide the push/pull type output for controlling external gate driver circuits. Since the range is 24 Vdc, a 10 ns rise/fall time for the HSDO output drivers is actually extremely fast when you consider the entire signal chain. Think of the HSDO outputs as a MOSFET half-bridge that either pulls up hard to Vext or down hard to GND.
The output termination for the HSDO is an area for which we need feedback from the community. Our preference is to include a 100 Ohm series termination resistor on the GPIC; this will ensure good signal integrity from the GPIC, across a ribbon cable to the gate driver, but it does slow down the slew rate considerably for the use case of a SEMIKRON SKiiP 3 IPM. In that case, because of the low impedance of the SKiiP 3 IPM driver, you can expect a rise/fall time of 500 ns for 24 Vdc or 250 ns for 12 Vdc (the logic threshold for SKiiP 3). Take for example a connection circuit schematic shown below.
With the 100 Ohm series resistor on the HS DO, the waveforms are well behaved- overshoot and ringing is eliminated and cross talk to adjacent HSDO signals is low. See the simulated and actual measurements below. Note: The slower rise time can be compensated for digitally in the FPGA in the digital PWM generation algorithm. If you know the delay, you can send the gate command signal early to effectively eliminate it. At a constant temperature, the delay will be relatively constant (perhaps only a few nanoseconds of variation).
On the contrary, if we eliminate the 100 Ohm series resistor, you will have to design an impedance matching AC termination scheme to avoid significant overshoot and ringing.
The push-pull driver circuit of the HSDO has a rise/fall time of ~10 ns. These signals propagate through relatively long ribbon cables that have a characteristic impedance of 60 to 100 Ω. Unless the proper termination scheme is used, impedance mismatch between driver, cable and receiver will induce reflections. These reflections will lead to voltage overshoot and ringing that can cause a variety of problems, including damage to receiver electronics, radiated emissions that could impact other signals, and reflections that degrade the timing certainty of switching instant and reliability. To make it clear, below I'm showing the same circuit without a 100 Ohm series resistance included on the GPIC HSDO.
As you can see, that type of ringing is completely unacceptable. You can see that the low impedance of the 1 nF capacitor on the SKiiP Driver inputs is the main cause of the problem. That's much larger than you would see on a typical CMOS Receiver, which typically has a 5 pF input capacitance. For applications that need a rise/fall time of 10 ns, it can still be achieved with the 100 Ohm series resistor as long as your receiver circuit has a high impedance. The circuit and simulation waveforms are shown below.
The rise/fall time of 10 ns is preserved and the signal integrity will be good. However, due to the very fast edge rate on the cable, cross talk and radiated energy could be a challenge.
Therefore, my opinion is that we should include the 100 Ohm series termination resistor. Any objections?
Are there any applications that absolutely demand that the HSDO output have 0 Ω output impedance?
Here is what it would like like in that case, with the requirement that you provide your own AC termination scheme such as the 100 Ω/100 pF termination shown below. I worry about asking every customer to create their own AC termination scheme like this. But... we definitely want feedback if this is what someone would like us to remove the 100 Ohm series resistor. Doing so would also significantly increase the current drive capabilities of the HSDO; likely to around 0.5 A/channel.
Big thanks to the NI R&D engineers that provided these simulations and measurements to help us all understand the tradeoffs.
Please share your thoughts and opinions, or just reply with a vote; either:
- YES: Include the 100 Ohm series resistor on HSDO, or
- NO: Do not include the 100 Ohm series resistor on HSDO
02-26-2012 02:47 PM
Thanks Brian,
For a very comprehensive reply. A small note in the document with respect to the receiver type, i.e., capacitance, impedance and propagation delay in the connection, would probably make sense. It would help distinguish in between ideal, high impedance, case when fast transients can be achieved and the real IGBT driver where specific limitations are in place.
In my opinion 100 ohms resistance at HSDIO is a must have, not only from the signal integrity point of view, but as a trivial protection mechanism.
------- Some other thoughts on the subject -------------
For some very high-speed or high-precision application 100 ohm may be too large. However, I don’t think that this particular board was designed for those applications anyway. The AD converters fall short on both sampling rate and resolution/accuracy to cover this range of applications (for audio amplifiers 192kHz sampling rate is a must and for precision one would probably look for ADCs with 16bit resolution or higher).
Connecting and external ADC on direct FPGA DIO solves the problem of course, but it would be reasonable to increase the number of connections to at least 30 in this case (I have been working on several amplifiers and we used from 16 to 28 lines).
05-16-2012 03:32 AM
There are designs now for bi-directional inverter/rectifiers. Can the new invert controller be used for this to provide the control electronics for this design. Essential we want to develop a bi-directional power block that can convert ac to dc and dc to ac with a capacity of 7.5 kW and dc voltages 500V to 2kV,
ac to 110 to 440 Vac.
05-16-2012 06:24 PM
The naming of the NI general purpose inverter controller is a little confusing. Actually, it's suitable for all inverter/converter switched-mode power supply (SMPS) applications and topologies. We have customers who are developing systems based on the NI GPIC for a wide range. For example, bi-directional inverter/rectifiers like yours such as back-to-back inverters (AC to DC to AC) for grid-tied motor/generators, i.e. wind turbines, 3-leg (6 pack) inverters, i.e. solar inverters, commercial electric vehicle propulsion drives, uninterruptable power supplies (UPS), railway power bus inverters/converters (not traction control), and so on. It's a pretty wide range of industries and applications. Also, by the way, due to the FPGA, a RIO based inverter controller like the NI GPIC can actually be reconfigured to adapt to different series/parallel wiring configurations by loading a new software personality. The NI GPIC is designed to be cost effective for all SMPS designs that are 50 KW or larger, so my only concern is whether it would hit the price target for your 7.5 kW power block. If your unit volumes per order are high we could evaluate whether a depopulated version of the NI GPIC would be appropriate. Generally though, we want to move as much volume through the standard GPIC configuration because driving high volume through a single part number lowers the cost in a way that benefits all customers. We also incentivize large orders on scheduled OEM contracts with 3-month lead time because large scheduled orders reduces our manufacturing cost and creates efficiencies in our production so we can share the savings back with you.
05-17-2012 04:24 AM
Thanlyou for your feed back. Has an indicative price been announced yet?
05-18-2012 04:32 PM
No, but if you or others in the community would like to discuss your application please shoot me an email (brian.maccleery@ni.com). Also, I should mention that the engineering design files (CAD files, connector pinouts, signal information,etc.) needed to create your GPIC mating board are now available for approved beta customers.
06-26-2012 11:16 PM
Hi Brian,
Exciting product, which, going by the pre-production data sheet hits the sweet spot for a project that is starting to gain some momentum, but I have a few questions.
What kind of release will the GPIC have, standard? (i.e. Globally available) OEM? (i.e. available only to customers purchasing bulk lots) or will there be a 'inverter' starter kit made available? Also can you give any hints about when the unit may be ready for release? and what exactly are the requirments to be included in the beta testing program?
Cheers
Martin
06-29-2012
09:25 AM
- last edited on
05-09-2024
03:49 PM
by
Content Cleaner
Hi Martin,
Sorry for the slow reply. Hectic! We are happy to say that the first GPIC beta board is in customer hands with more arriving to customers today.
The release of the NI sbRIO GPIC will be a global product release with global availability. Our plan is to launch the general purpose inverter controller at NIWeek on August 7th, 2012 with a main stage keynote and technical sessions in the NIWeek Energy Technology Summit- Designing the Smart Grid. If everything stays on track, the GPIC will be orderable for high volume OEM production by mid to late August, 2012.
We do plan to offer an evaluation kit that is only orderable quantity one (for evaluation only) and includes the following:
For commercial OEM deployment, the NI 9683 GPIC board and NI sbRIO-9606 will be sold in a kit containing 20 boards. This OEM deployment kit will contain the following:
Pricing discounts are generally tied to the number of units purchased in the scheduled OEM contract order, since our manufacturing costs are significantly reduced when a larger build sizes are executed and the order is scheduled in advance. Generally speaking, the GPIC stack (NI 9606+9683) is cost effective for grid-tied SMPS power converter designs rated at 50 kVA or larger up into the 10,000 unit/year range. For at least two high volume OEM customers so far, the GPIC stack has been significantly less expensive than in-house custom DSP/FPGA board designs from a recurring bill of material (BOM) cost perspective. If necessary, we can take other steps to cost optimize such as creating a depopulated version of the GPIC board for high volume OEMs, but so far that has not been necessary and in general we prefer to drive volume to the standard product since all customers benefit from the cost benefits of leveraging a standard design.
In terms of non-recurring engineering development cost (NRE), going with the GPIC and NI graphical system design toolchain is strikingly less expensive. UBM/EETimes recently sent their embedded market survey to around a thousand NI LabVIEW FPGA/RT RIO embedded systems development teams. The survey results for the items below (margin of error +/- 3.9-4.3%) show a stark difference between the performance metrics and development cost for LabVIEW/RIO teams compared to the general/traditional embedded systems market (typically text based programming tools and full custom PCB design). For example, the average NRE to complete the embedded design is 30 person-months for LabVIEW/RIO teams compared to 144 person-months for the overall embedded market. Assuming skilled embedded developers costing $100k/year with overhead (facilities, health care, etc.), the average LabVIEW/RIO embedded systems design project costs $250k compared to $1.2M for the overall embedded market- an average NRE cost savings of $950k per design.
|
NI Embedded Customers (2012)1 |
EETimes Overall Embedded Market (2012)2 |
Ratio |
Average Development Team Size (HW, SW, Firmware Engineers) |
4.8 |
11.5 | 2.4 |
Average Months to Complete Project |
6.2 |
12.5 | 2.0 |
Average Person-Months to Complete Project |
30 |
144 |
4.8 (average of 114 person-month savings per design) |
Average Development Cost (assuming $100k/person/year including overhead) |
$248,000 |
$1,198,000 |
4.8 (average $950,000 cost savings per design) |
Percent of Projects Completed On or Ahead of Schedule |
58% of NI customers |
42% of embedded market |
0.7 |
Percent of Projects Completed Behind Schedule/Late |
38% of NI customers |
55% of embedded market |
1.4 |
NOTE1: The EETimes study was a global Email/web study including over 1,700 responses from embedded engineers from Americas, Europe and Asia
NOTE2: The NI study was a global Email/web study including over 1,000 responses NI embedded customers from Americas, Europe and Asia
Compared to traditional embedded design teams, NI RIO and LabVIEW FPGA/RT embedded systems design teams:
o Complete projects in half the time as EET developers do (average 6.2 months for LabVIEW embedded designs versus 12.5 months for overall embedded market)
o Complete more projects on or ahead of time with fewer late projects (58% of LabVIEW embedded designs complete on or ahead of schedule versus 42% for overall embedded market)
o Complete projects using a team that is 2.4 times smaller (average of 4.8 compared to 11.5 embedded HW/SW/Firmware engineers)
o Complete projects with 114 fewer person-months of non-recurring engineering (NRE) development cost
o Are younger and less experienced (fewer years out of school)
Regarding criteria for the GPIC beta program, here are the high level goals of the program:
Please email me if you are interested in applying and I can provide more details (brian.maccleery@ni.com).
Best Regards,
Brian MacCleery