Slide Deck - New Platform and Method for System-Level Design of Next-Generation FPGA-based Digital SMPS

[BMac]

This presentation introduces the NI R&D investments in both embedded design and real-time test technology to complete the "Design V" for power electronics, the evolution of FPGAs to include mini hardcore DSPs inside, design goals and guidelines for the new design method, a demonstration of the new FPGA/SMPS co-simulation toolchain, and how Moore's Law is driving more embedded teams to adopt a chip-on-board design with fully integrated graphical system design tools rather than facing the cost, risk and delays of full custom design.

Topics:

• NI R&D investments in both embedded design and real-time test technology to complete the "Design V" for power electronics
• The evolution of FPGAs to include mini hardcore DSPs inside, making them the ideal target for power electronics control
• Design goals and guidelines for the new design method and platform
• A demonstration of the new FPGA/SMPS co-simulation toolchain
• How Moore's Law is driving more embedded teams to adopt a chip-on-board design with fully integrated graphical system design tools rather than facing the cost, risk and delays of full custom design

Highlights:

You can also find a pre-recorded IEEE Spectrum webcast version of this material here:

A New System-Level Design Methodology and Platform for FPGA-based Power Electronics Control