5644R Acq class LO rejection

[JÞB]

OK guys, That was a fun one to find.

My SDR was generating CW at Freq(x) and power level y.  Hmmmm.   the VST seams to like to reject that center freq assuming it to be LO blead.  offsetting the Acq center freq "Found" the actual output of my radio.  Back to the drawing board for "Spectral Stitching"  CW might just be applied.

[James_D]

Good morning Jeff,

Sorry to hear you're running into some trouble. I've spoken with some of my colleagues about this and we'd like to take a closer look at the problem you're encountering. In particular we would like to know the frequency and power level you were generating at. Also, were you using RFSG/A or the Instrument Design Libraries?

Thanks,

James Duvall

VST Product Support Engineer

[JÞB]

My Software defined Radio was generating CW 220MHz @-20 dBm.  I was using Read Spectrum.vi from the Host Acquisition class and setting the center freq to 220MHz span 50kHz RBW 100Hz.  I observed readings close to -60dBm untill I offset the span by 10kHz.  I then saw my CW signal at -20dBm.  No, this does not happen on RFSA because of the spectral stiching used to simulate LO Rejection.

Like I said- Fun to find (there's a few hours trobleshooting I won't get back soon)

[James_D]

Hi Jeff,

So it sounds like you're using VIs from the Sample Project. We used a 5673E generating at 220 MHz, -10 dB. For the VST we used a 220 MHz center frequency, 50 kHz span, and RBW of 100 Hz and we're able to see the signal without an offset. Also, there is no LO Suppression in the sample project. Is there some facet of your configuration that you can think of that we might be missing in trying to replicate the problem you're facing?

[JÞB]

Yes, my version of the driver is not public. apparently you all had a better thought for release. glad too hear.

[JÞB]

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@James_D wrote:

Hi Jeff,

So it sounds like you're using VIs from the Sample Project. We used a 5673E generating at 220 MHz, -10 dB. For the VST we used a 220 MHz center frequency, 50 kHz span, and RBW of 100 Hz and we're able to see the signal without an offset. Also, there is no LO Suppression in the sample project. Is there some facet of your configuration that you can think of that we might be missing in trying to replicate the problem you're facing?

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Actually, Now that I'm on a desktop and not a mobile device, I can see your picture more clearly.

Your devices aren't sharing a 10MHz ref are they?  There is a slight offset from center freq.  Tune the generator slightly down in freq so it appears at the analizer center freq and see if that shows what I saw.

[James_D]

Hi Jeff,

We ran a couple more tests. First is a loopback test:

freq: 220MHz pwr level: -10dBm span: 2k rbw: 20 

We used the onboard clock in this case.

The above graph used a 5673E for generation and acquired with the 5645R.

freq: 220MHz         pwr level: -10dBm       span: 2k     rbw: 20

Both units drew on the PXI backplane's 10 MHz clock.

In both cases we didn't see any rejection.

You said before that you're using the beta version of the driver. Do you have a system you could test your code on that is running the newest version of the driver?

Thanks,

James Duvall

[JÞB]

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@James_D wrote:

Hi Jeff,

We ran a couple more tests. First is a loopback test:

freq: 220MHz pwr level: -10dBm span: 2k rbw: 20 

We used the onboard clock in this case.

The above graph used a 5673E for generation and acquired with the 5645R.

freq: 220MHz         pwr level: -10dBm       span: 2k     rbw: 20

Both units drew on the PXI backplane's 10 MHz clock.

In both cases we didn't see any rejection.

You said before that you're using the beta version of the driver. Do you have a system you could test your code on that is running the newest version of the driver?

Thanks,

James Duvall

---

That's a good enough test for me.  And, unfortunately I'm loosing access to my dozen VST's at a very rapid rate while they are hitting the production floor!  I don't dare suggest swapping drivers on a system at this point.

I will track the issue for the continuing engineer.

and not just "The" Beta version A "built for us" version that has some features and not others- and a few changes tossed in by me to play nicer with the Mod and SM Toolkits (no changes to FPGA)  Its been a wild ride but worth it.

[ASEAN]

Hi Jeff,

Can you confirm if you are using a reference clock source on the program code of your VST and your RF Sig Generator ?

Make your source and the measure use the same reference clock: PXI_Clk

I tried a 5652 (RF Sig Gen) as the source and 5644R as the measure and verified the effects of using the Onboard_Clk and PXI_Clk.

See attached.

Regards,

James

[JÞB]

My RF gen, as I said, is a software defined radio "UUT."   The Radio's 440MHz LO TCXO was tuned using the same external Rb Ref (to agree within >1Hz ) that the VST is hooked up to and using. 

So, yes, I'm "Using" the same external reference.  The CW RF from my radio at 220MHz and the Spectrum bin from the VST Acquisition with 10 Hz binning should agree.  Phase may be arbitrary- but the result repeated across UUTs (and their power on times) and VST's (all hooked to the same 10MHz standard through different cables).

To repeat, if you cannot reproduce this on customer facing software-  and I think you were unable too, your latest method seams reasonable to reproduce what I saw, just go ahead and close the report here.  If nothing else, the workaround to deliver is found and very few customers will be running on the exact same driver. 

Spoiler

(OK, Just me but, I'm important!)