5660 accuracy for hopping signal

[adnan_fazil]

Thanks Chris

          I m going to start the LabVIEW FPGA now.But before that i want to know that  is it necessary to connect the clock output of PXI-5600 to the clock input of PCI-5640R, as i am using the cards without connecting the clock from PXI-5600 to PCI-5640R? If this connection is necessary then kindly let me know the part number of the required cable (keeping in mind the distance, between the SMA connector on PXI-5600 for clk signal out and SMB connector on PCI-5640R for clk signal in, that is almost 45 cm in our configuration).

Thanks in advance

BEST REGARDS

ADNAN

[Chris_W.]

Good question, and I'm sorry I think I forgot to address this in my last post. Whether or not to connect the 10MHz clock out of the 5600 to the Clock In of the 5640R is kind of up to you. If you do connect it, you would see an increase in frequency accuracy of the 200MHz timebase of the 5640R, which if you're going the absolute best performance possible, would likely be a good idea.

The clock accuracy of the 5600 is quite a bit better than the 5640R (50ppb vs. 25ppm), and because the 5640R will PLL it's 200MHz clock to any clock signal between 1MHz and 100MHz in 1MHz steps (you can find this in the 5640R specifications), you would benefit from this connection.

As for cabling, NI doesn't have an SMB to SMA cable that will reach 45cm. There is an SMA100 cable that you can get a 45cm SMA to SMA cable and just purchase an SMA to SMB converter. I did a quick google search for the connectors and you can see there are a bunch of options HERE.

Since I'm sure it will take you a little bit of time to get the cable/adapter, I would certainly not wait to start developing your code. The only difference you'll have in the code when you do connect the clocks will be the addition of the ni5640R Configure Ref Clock.vi. So, it should be a smooth transition when you're ready.

Chris W

[adnan_fazil]

THANKS CHRIS

       As advised by you, i m working on the example program called ni5640R Analog Input, but in the processing loop i am unable to insert the FFT/windowing in the subVI that is listed as "place your code here." I cant see any FFT express or Subvi in the functions palatte for LabVIEW FPGA. i am using labview 8.2. 

Kindly guide me how i can do FFT/Windowing in the LabVIEW FPGA VI using LabVIEW 8.2?

Secondly, u said in one of ur previous post , "I would take a look at the Developer Zone example that I posted a couple posts ago, which performs a spectrum acquisition on the 5641R. The FPGA code in this example does almost everything you would want to do. You'll notice that it acquires data continuously, then Windows it and takes the FFT and sends it back to the host. This VI also already does a peak search, but the only thing you would need to do is to pass back the peak search and the calculate the frequency of that peak and pass just that information back to the host to be written to a file."

Kindly send me the above mentioned code.THANKS IN ADVANCE

REGARDS

ADNAN FAZIL 

[Rashid931]

Thanks a lot, Chris W.

Kindly send me the same code for Labview 2009 as requested by Adnan Fazil.

Thanks and Regards.

Rashid 

[Chris_W.]

The code for this demo is posted on those two pages I linked in my previous post HERE is the code for LV 2009 using a PXIe-5641R. Since you are using a 5640R, Rashid, you'll need to change the device in the project and recompile the code for the 5640R.

Adnan, I didn't realize you were working in LV 8.2. This actually presents a bit more of a problem, since the FFT and most windowing functions were introduced to the LV FPGA Module in 8.5 or 8.6. So, you may actually have to create your FFT algorigthm manually or you might be able to find some IP on the community site or on IPNet.

I don't know of another good way to determine a the frequency of a signal in a point by point method on the FPGA without doing the FFT first. Adnan, do you perhaps have the availability of LabVIEW 8.6 or 2009? This would make things much easier. Also, the code that I mentioned above is only for LabVIEW 2009, so I don't have a copy of that code for 8.2 due to all the things I mentioned. If that's not an option, you may have to do some research on other ways you could process that data on the FPGA to determine the frequency.

[Rashid931]

Thanks Chris as you are always ready to help and guide.

In your last post, you said that

"The code for this demo is posted on those two pages I linked in my previous post HERE is the code for LV 2009 using a PXIe-5641R. Since you are using a 5640R, Rashid, you'll need to change the device in the project and recompile the code for the 5640R."

Kindly let me know that how i can change the device in the project? I have to add a new target i.e. 5640R and build new FPGA VI completely ? OR There is some simple method to just change the target device in a simple way? 

Waiting for your Kind reply.

Thanks and Regards,

Rashid

[Chris_W.]

You will need to create a new 5640R target in the project that you download from that link and then copy everything from the old 5641R  target into the new 5640R target.

Once you've added the new target and copied the correct configuration/FPGA VI over to the new target you can delete the old 5641R target from the project and re-compile the FPGA VI for the new 5640R target. Once you've got all things copied to the new target and deleted the old target your project should look identical to the old one except the name of the target should reference the 5640R as its "Target Type" which is the name farthest to the right in parenthesis.

Message Edited by Chris W. on 05-25-2010 02:50 PM

Message Edited by Chris W. on 05-25-2010 02:53 PM

[Rashid931]

Thanks Chris.

            You are really a great man.

Rashid

[Rashid931]

Thanks a lot Chris.

In the spectrum_analyzer_5641r.zip, the original FPGA Target (PXIe-5641R) has four clocks i.e.

(1)   40 MHZ Onboard Clock 
(2)   PXIe_Clk100
(3)   ADC_0_Port_A_Clk
(4)   Configuration_Clk

but when I add FPGA Target (RIO0,PCI-5640R), then first two clocks are not available.

Kindly guide me what could be the best replacement clocks in case of FPGA Target (RIO0,PCI-5640R) in lieu of the first two clocks of FPGA Target (PXIe-5641R)?

Secondly, how I can run FPGA VI in Emulation mode in Labview 2009 so that I can run FPGA VI before compiling it?

Thanks and Regards,
Rashid 

[Chris_W.]

Hi Rashid,

You have a couple of options here. The PXIe-Clk100 is only available for PXIe devices in a PXIe chassis, so this clock won't be available, but this project doesn't actually use this clock, so we don't need to worry about it. You are correct that there is no 40MHz Onboard Clock on the 5640R, but we should be able to replace that clock with the RTSI_Ref_Clk. The 40MHz Onboard Clock is there so that we can derive an 80MHz clock to use for the two processing loops of the FPGA VI. However, the 40 MHz clock can be used as well and the VI will run just fine. The RTSI_Ref_Clk is a divide down of the 200MHz VCXO on the PCI-5640R, so we compile the RTSI_Ref_Clk for a frequency that we want to use to control the rate of the two processing loops on the FPGA VI. Here's an image from the 5640R help that shows the clock connection to the FPGA VI:

To create this clock properly right click the 5640R target and select New»FPGA Base Clock. In the properties for this you can select the radial button to compile for single frequency  and specify to compile it for 40MHz or 80MHz, either will work. You can play with the frequency that you would like to run your processing loops at.

Chris