PXIe-5646R example "5646R RFSG Synchronization" -Error -366056

[wdvihv]

Hi,

We have a PXIe-1085 chassis equipped with four PXIe-5646 ( slot 2, 5, 11, 14). 

To  synchronize any two of these four 5646, we run the example "5646R RFSG Synchronization"

When choosing slot2 and slot 5(first and second pxie), there is no errors.

However, when we replace one or both , we got an error

We have an external LO, so we disabled the 'LO out enabled' and make 'LO IN ' as LO source for both master and slave device.

Reference Clock Source: PXI_CLK

Frequence: 868MHz

error -366056 

Raisons possibles : The device failed to detect whether its Sample Clock is synchronized. Check whether the Sample Clock sync signal is being provided and the Reference Clock is connected properly.

I cant understand why it's ok four the first two slots but have errors for others as nothing changes.

Thank you a lot if you have a idea.

Best regards

Yanni 

[Captain_K]

Hi Yanni,

I don't do much with our RF hardware, but because the 1085 has multiple trigger buses and you're using static trigger routing (calling out which trigger lines to use in LabVIEW), you need to manually make the connections across different trigger buses.

The 1085 has 3 trigger buses per the manual.

You can make these connections in MAX or in LabVIEW. MAX is easier, just remember to hit save. This KB explains how to do this.

Basically, whichever module is providing the sample clock, look at what slot it's in, and connect the trigger buses in MAX so that triggers are routed away from that trigger bus.

[yentinh90]

Thank you very much Captain_K. Your reply really helps.

Yanni