Trigger IF-RIO 5641R and Digitizer 5142

[dsangree]

Sorry I didn't see your post sooner.

The reason why you have to run the ni5640R Configure RTSI.vi is that there is internal routing that has to happen within the IF-RIO. Essentially the PXI backplane is not directly connected to the FPGA. It goes through an intermediate MUX/DEMUX, which handles the routing. This routing is controlled by the ni5640R Configure RTSI.vi.

Also, this VI controls the direction of these lines which is why you could not output until you ran it. Changing to read/write on the FPGA VI does change the direction of the FPGA pins, but you also have to change the direction of the lines connecting the FPGA to the PXI trigger lines within the IF-RIO.

[philippe_w]

Simon,

It would be convenient if we could automatically change the input/output direction on those pins, but the FPGA diagram does not have access to re-configure that from the diagram.

The read/write settings on the IO node determines how the FPGA image is compiled and is able to configure the pins on the FPGA itself, but those trigger lines pass through a bus interface chip before going to the backplane connector. The FPGA diagram doesn't have a way to change the registers in that bus interface chip; its configuration interface is only exposed to the host. So, it must be a host-side VI that configures the directions and routing.

On other devices, like digitizers you mentioned, the VIs that are configuring the triggering are indeed running from the host and can control all of the chips involved. They can set up the routing as well as configure the hardware to use or drive those lines. On the 5640R and 5641R devices, we need a combination of the host-side VI plus the right behavior in the FPGA.

I hope that clears things up!

~Philippe