We know that the 9262 has the capability to update AO at 1MSa/sec, but if we use the FPGA I/O node to direct-write data to the node, the max update rate is around 600KSa/sec, and the User I/O mode is much more complex.
I found out by simply set the FPGA Target's Main clock to 80M or even higher, we can reach an update rate above 860KSa/sec, which is better than the shipped example of about 660KSa/sec.
This simple trick might also work on 9223 which is a 1MSa/sec ADC, I also wonder if it will work for 9775, if it can transmit data triple faster it would be a decent HighSpeed C-module for CRIO.
