Accessing the 40MHz clock on the PXI-7831R FPGA Module

[B.Settles]

How do you access the 40MHz clock on the PXI-7831R FPGA Module?

I'm trying to the FPGA to do RS-422 communication with UART and HDLC protocols. I want to divide the clock signal to generate the necessary baud rates. I've downloaded the FPGA serial examples as a start, but I'm looking for a direct connection to the 40MHz signal.

I'm Using LabVIEW 7.1 and FPGA Module 1.1 with the LabVIEW Embedded Project Structure.

[Bassett_Hound]

settlesj,

If you are looking to have access to a 40MHz digital signal,  it is possible to generate and acquire one using 7831R and LabVIEW FPGA module.  To do this you would need to take advantage of the different compile speeds available with the FPGA module. The available compile clock frequencys are: 40MHz, 80MHz, 120MHz, 160MHz, 200MHz

For example to generate a 40MHz pulse train you could compile with 80MHz clock frequency (2 clock pulses are needed for a square wave period).
You will have to be careful when generating code because compiling with a clock frequency higher than the default one (40MHz) could give compile errors in some cases. These errors could happen more frequently if the code is more complex and needs more time to be executed.

I have attached an example program that generates a 40 MHz signal on a digital line.  From there you could divide down the clock rate to which ever specified baud rates you needed.  As a side not the LabVIEW FPGA 8.0 Module added the ability to derive additional clocks from FPGA base clocks in a LabVIEW project.  Hope this helps.

Steven B.