09-16-2009 04:18 PM
Basically, I am having issues getting a DMA FIFO based transfer method to compile. For some reason, I can only use two of the three FIFO's at any given time or I get a compilation error.
If I use a connector block transfer method, there is too much information to process within the SCTL and it generates a timing error in compilation.
I have already disabled non-necessary functions in the FPGA in an attempt to get this to work one way or the other...
Any input is appreciated. Thanks!
09-17-2009 02:52 PM
Hello which hardware are you using and which versions of the software? Also, what is the reason for failure given by the compiler?
Thanks,
Anna K.
09-17-2009 02:58 PM