Block exponent signal - Xilinx FFT v7.1 - FlexRIO - FPGA

[Badri15]

I am using Xilinx FFT v7.1 IP (FPGA - NI 7965R, LabVIEW 2012). I am computing the FFT of 16 bit real signed integer.

Is 5 bit  block exponent signal in block floating point FFT in Xilinx FFT v7.1 module signed or unsigned? The pdf document talks about right shift of the output data to utilize the dynamic range, doesn't mention about left shift nor gives enough details about it.

Is there a base value like in IEEE floating point format that I need to use to find the correct output value?

[JLewis · Accepted solution]

I would assume it's unsigned unless you have observations to the contrary. The baseline behavior is to retain left bits to prevent overflow, so the scaling always involves shifting right when you think some of the most significant bits will be unused. They do provide an example of b00101 = 5, so that indicates there is no exponent bias to be applied.

[Badri15]

This is my first time working with block floating point FFT. I thought so, but I wanted to confirm it prior to optimizing my design for memory usage and performance speed.

Thanks for your help.