I am currently trying to log some voltage data into a measurement file using Compact RIO with a NI 9201 module. I wrote my FPGA and Host VIs from scratch and am now wondering why all the examples do things in a different way (while my approach seems to not work).
The concept seems to be that calibration data is read from the module, then it is commonly written to the FPGA VI front panel and this is then read by the host VI. Now, in all examples in the Host VI a while loop is used to wait for the calibration data to become available. I thought, I'd be clever and instead assert an interrupt in the FPGA VI once calibration data is read, make my Host VI wait for this, subsequently read the calibration data an then acknowledge the interrupt. My thought was that this would be the best way to make sure the both VI start reading data and transferring it into the measurement file at the same time.
Can someone explain me what is wrong with my concept and why my VIs aren't working as I would expect them to work? I attached the Host VI to illustrate my (bad) idea.
